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PC Card Controller compliant with PCMCIA 2.1/JEIDA 4.2
RF5C296/RF5C396L/RB5C396/RF5C396
APPLICATION MANUAL
ELECTRONIC DEVICES DIVISION
NO.EA-028-9804
NOTICE
1. The products and the product specifications described in this application manual are subject to change or discontinuation of production without notice for reasons such as improvement. Therefore, before deciding to use the products, please refer to Ricoh sales representatives for the latest information thereon. 2. This application manual may not be copied or otherwise reproduced in whole or in part without prior written consent of Ricoh. 3. Please be sure to take any necessary formalities under relevant laws or regulations before exporting or otherwise taking out of your country the products or the technical information described herein. 4. The technical information described in this application manual shows typical characteristics of and example application circuits for the products. The release of such information is not to be construed as a warranty of or a grant of license under Ricoh's or any third party's intellectual property rights or any other rights. 5. The products listed in this document are intended and designed for use as general electronic components in standard applications (office equipment, computer equipment, measuring instruments, consumer electronic products, amusement equipment etc.). Those customers intending to use a product in an application requiring extreme quality and reliability, for example, in a highly specific application where the failure or misoperation of the product could result in human injury or death (aircraft, spacevehicle, nuclear reactor control system, traffic control system, automotive and transportation equipment, combustion equipment, safety devices, life support system etc.) should first contact us. 6. We are making our continuous effort to improve the quality and reliability of our products, but semiconductor products are likely to fail with certain probability. In order prevent any injury to persons or damages to property resulting from such failure, customers should be careful enough to incorporate safety measures in their design, such as redundancy feature, fire-containment feature and fail-safe feature. We do not assume any liability or responsibility for any loss or damage arising from misuse or inappropriate use of the products. 7. Anti-radiation design is not implemented in the products described in this application manual. 8. Please contact Ricoh sales representatives should you have any questions or comments concerning the products or the technical information.
June 1995
RF5C296/RF5C396L/RB5C396/RF5C396
APPLICATION MANUAL
CONTENTS
OUTLINE ......................................................................................................1 FEATURES ...................................................................................................1 APPLICATIONS .............................................................................................2 PIN CONFIGURATION (RF5C296) ......................................................................3 PIN ASSIGNMENTS (RF5C296) .........................................................................4 PIN CONFIGURATION (RF5C396L/RF5C396) .........................................................5 PIN ASSIGNMENTS (RF5C396L/RF5C396) ............................................................6 PIN CONFIGURATION (RB5C396) ......................................................................8 PIN ASSIGNMENTS (RB5C396) .........................................................................8 PIN DESCRIPTION ......................................................................................11
.........................................................................................11 2. Card Slot Interface ........................................................................................13 3. Other Control Pins ........................................................................................15 4. Power and Ground Supply Pins .........................................................................16 BLOCK DIAGRAM .......................................................................................17 FUNCTIONAL DESCRIPTION .......................................................................18 1. Address Mapping .........................................................................................18 2. Power Management ......................................................................................19 3. Mixed Voltage Operation .................................................................................19 4. Address Mapping .........................................................................................21 5. Bus Sizing ..................................................................................................21 6. Internal Register Access ................................................................................22 7. Plural Slots System .......................................................................................23 8. PCMCIA-ATA Mode .......................................................................................24 9. DMA Mode .................................................................................................25 INTERNAL REGISTERS ...............................................................................27 1.Chip Control ................................................................................................27
1. ISA Bus Interface
2. I/O Mapping ................................................................................................36
.........................................................................................38 4. Expansion Function .......................................................................................41 5. I/O Address Remapping..................................................................................42 6. Summary of Internal Register ...........................................................................44 HARDWARE DESIGN CONSIDERATIONS .....................................................46 1. Initial Value Setting Pins .................................................................................46 2. Connections to System Bus .............................................................................47 3. Connections to PCMCIA Slot ............................................................................50 4. Connections to Power Supply System .................................................................51 5. Connecting Multiple Units of RF5C296 or RF5C396 .................................................53 SOFTWARE DESIGN CONSIDERATIONS .....................................................54 1. Confirmation of Access to Internal Registers ..........................................................54 2. Identification of PC Card Types .........................................................................54 3. Address Mapping and Address Window Setting ......................................................54 4. Interrupt Processing ......................................................................................62 5. Card Slot Pin Status Indication and Register Setting.................................................65 ABSOLUTE MAXIMUM RATINGS .................................................................70 DC CHARACTERISTICS ..............................................................................71 AC CHARACTERISTICS ...............................................................................73 1. 8/16bit Memory Cycle ....................................................................................73 2. 8/16bit I/O Cycle ..........................................................................................76 3. Internal 8bits Register Access Cycle ...................................................................79 4. Interrupt, Ring Indicate Speaker ........................................................................80 5. Reset from POWERGOOD ..............................................................................81 6. DMA Read Cycle Timing .................................................................................82 7. DMA Write Cycle Timing .................................................................................83 8. DMA Request Timing .....................................................................................84 BUS SYSTEM ..............................................................................................85 SUPPORT ENVIRONMENT...........................................................................85 PACKAGE DIMENSIONS ..............................................................................86
3. Memory Mapping
COMPLIANT WITH PCMCA2.1/JEIDA4.2 PC CARD CONTROLLER
RF5C296/RF5C396L/RB5C396/RF5C396
OUTLINE
The RF5C296, the RF5C396L, the RB5C396, and the RF5C396 are enhanced version of the RF5C266 and RF5C366, LSIs functioning as controllers for interfacing IC memory cards, modems, and I/O cards, such as HDDs, to system buses in compliance with the PCMCIA2.1 or JEIDA4.2 Standard. These controller LSIs can be used to configure an ISA bus system which supports PC cards. The RF5C296 supports one PC card slot while the RF5C396L, the RB5C396 and the RF5C396 support two PC card slots. Incorporating a buffer and a transceiver, each of these devices can be directly coupled to the ISA system bus and the PC card slots. The devices are also capable of providing an independent power supply of 3.3V or 5V for each slot interface, system bus, and core logic. Further, they effect substantial space savings through implementation in slimline packages (i.e. the 144pin LQFP for the RF5C296, the 208pin LQFP for the RF5C396L, the 256pin PBGA for the RB5C396 and the 208pin QFP for the RF5C396). Unless otherwise noted, the RF5C396L, the RB5C396 and the RF5C396 are collectively referred to as the RF5C396 in this manual.
FEATURES
* Enhanced version of RF5C266/RF5C366 * DMA mode support * Enhanced power management * INPACK# pin support * Available in thin (t=1.5mm) LQFP and PBGA * Compliant with PCMCIA2.1/JEIDA4.2 * i82365SL B_Step compatible register set * Direct connection to PCMCIA2.1/JEID4.2 PC Card slot * Easy host interface using ISA I/O addresses 3E0h, 3E1h * Direct connection to ISA Bus * Programmable IRQs to level mode or edge trigger mode * Enhanced Power Management based on socket and window inactivity * PCMCIA-AT-A Disk interface support * 8bit cycles follow SBHE# independent of programmed window size * 5 programmable memory windows per slot * 2 programmable I/O windows per slot * 3.3V & 5V Mixed Voltage Operation * DMA mode Support
1
RF5C296/RF5C396L/RB5C396/RF5C396
* PACKAGES * RF5C296 * RF5C396L * RB5C396 * RF5C396 144pin LQFP (t=1.7mm) 208pin LQFP (t=1.7mm) 256pin PBGA (23 23) 208pin QFP
APPLICATIONS
* PC (Notebook Type, Pen-based Type and Palm Top Type) * Docking Station * PDA * Handy Terminal
2
RF5C296/RF5C396L/RB5C396/RF5C396
PIN CONFIGURATION
* RF5C296 Pin Assignments (Top View)
IRQ3 SA7 IRQ4 SA8 IRQ5 SA9 SA10 IRQ7 SA11 SA12 REFRESH# SA13 SA14 SA15 SA16 IOR# IOW# AEN IOCHRDY GND SD0 SD1 ZEROWS# SD2 GND SD3 VCCAT SD4 SD5 IRQ9 SD6 SD7 POWERGOOD SPKROUT# INTR# RESETDRV
SA6 SA5 SA4 BALE SA3 SA2 SYSCLK SA1 SA0 MEMCS16# SBHE# IOCS16# LA23 IRQ10 LA22 IRQ11 LA21 VCC IRQ12 LA20 IRQ15 LA19 IRQ14 LA18 LA17 MEMR# MEMW# SD8 SD9 SD10 GND SD11 VCCAT SD12 SD13 SD14 100 110 90 80
VCC_AT
VCC_AT
70
120 60
VCC_CORE
130 50
140 40 144 1 10 20
VCC_SLOT
30
GND SD15 CD2# WP/IOIS16# CD10 CD2 CD9 CD1 CD8 CD0 BVD1/STSCKG# CA0 BVD2/SPKR# CA1 CA2 GND CA3 WAIT# GND CA4 VCCSLOT RESET CA5 CA6 CA25 CA7 CA24 CA12 CA23 CA15 CA22 CA16 CA21 RDY/BSY# CA20 WE#/PGM#
*)
CD1# and CD2# are powered by VCC_AT
VCC5EN# VPP_EN0 VPP_EN1 5VDET/GPI RI_OUT# VCC3EN# CS# REG# CD3 CD1# CD4 CD11 CD5 CD12 CD6 INPACK# CD13 VCCSLOT CD7 GND CD14 CE1# CD15 CA10 CE2# OE# CA11 CIORD# CA9 CIOWR# CA8 CA17 CA13 CA18 CA14 CA19
3
RF5C296/RF5C396L/RB5C396/RF5C396
PIN ASSIGNMENTS
* RF5C296
Pin No. Symbol Pin No. Symbol Pin No. Symbol Pin No. Symbol
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
VCC5EN# VPP_EN0 VPP_EN1 5VDET/GPI RIOUT# VCC3EN# CS# REG# CD3 CD1# CD4 CD11 CD5 CD12 CD6 INPACK# CD13 VCCSLOT CD7 GND CD14 CE1# CD15 CA10 CE2# OE# CA11 CIORD# CA9 CIOWR# CA8 CA17 CA13 CA18 CA14 CA19
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
WE#/PGM# CA20 RDY/BSY# CA21 CA16 CA22 CA15 CA23 CA12 CA24 CA7 CA25 CA6 CA5 RESET VCCSLOT CA4 GND WAIT# CA3 GND CA2 CA1 BVD2/SPKR# CA0 BVD1/STSCHG# CD0 CD8 CD1 CD9 CD2 CD10 WP/IOIS16# CD2# SD15 GND
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
SD14 SD13 SD12 VCCAT SD11 GND SA10 SD9 SD8 MEMW# MEMR# LA17 LA18 IRQ14 LA19 IRQ15 LA20 IRQ12 VCC LA21 IRQ11 LA22 IRQ10 LA23 IOCS16# SBHE# MEMCS16# SA0 SA1 SYSCLK SA2 SA3 BALE SA4 SA5 SA6
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
IRQ3 SA7 IRQ4 SA8 IRQ5 SA9 SA10 IRQ7 SA11 SA12 REFRESH# SA13 SA14 SA15 SA16 IOR# IOW# AEN IOCHRDY GND SD0 SD1 ZEROWS# SD2 GND SD3 VCCAT SD4 SD5 IRQ9 SD6 SD7 POWERGOOD SPKROUT# INTR# RESETDRV
*)
I : Active "low" signals are indicated by "#".
4
RF5C296/RF5C396L/RB5C396/RF5C396
PIN CONFIGURATION
* RF5C396L/RF5C396
IRQ10 LA22 IRQ11 LA21 IRQ12 LA20 IRQ15 LA19 IRQ14 LA18 LA17 MEMR# MEMW# SD8 SD9 SD10 GND SD11 VCCAT SD12 SD13 SD14 SD15 RI_OUT# BCD2# BWP BCD10 BCD2 BCD9 BCD1 BCD8 BCD0 BBVD1/STSCHG# BCA0 BBVD2/SPKR# BCA1 BCA2 BINPACK# BCA3 VCCSLOT#1 BWAIT# BCA4 BRES BCA5 BCA6 GND BCA25 BCA7 BCA24 BCA12 BCA23 BCA15 140 130 120 110
LA23 IOCS16# SBHE# MEMCS16# SA0 SA1 SYSCLK SA2 SA3 BALE SA4 SA5 SA6 IRQ3 SA7 IRQ4 SA8 IRQ5 SA9 SA10 IRQ7 SA11 SA12 REFRESH# SA13 SA14 SA15 SA16 IOR# IOW# BAEN IOCHRDY SD0 SD1 ZEROWS# GND SD2 SD3 VCCAT SD4 SD5 IRQ9 SD6 SD7 POWERGOOD SPKROUT# INTR# BVPP_EN1 BVPP_EN0 BVCC3EN# BVCC5EN# CS#
156 160
150
104
VCC_AT
VCC_SLOT#1
100
170 90
180 80
VCC_CORE
190 70
200 60
VCC_SLOT#0
208 1 10 20 30
VCC_SLOT#0
40 52
BCA22 BCA16 BCA21 BRDY/BSY# BCA20 BWE#/RGM# BCA19 BCA14 BCA18 BCA13 BCA17 BCA8 BCIOW# BCA9 BCIORD# BCA11 VCCSLOT#1 BOE# BCE2# BCA10 BCD15 BCE1# BCD14 BCD7 BCD13 GND BCD6 BCD12 BCD5 BCD11 BCD4 BCD1# BCD3 BREG# GND ACD2# AWP ACD10 ACD2 ACD9 ACD1 ACD8 ACD0 ABVD1 ACA0 ABVD2 ACA1 ACA2 AINPACK# ACA3 AWAIT# ACA4
*)
ACD1# ,ACD2# ,BCD1#,BCD2# are powered by VCC_AT
AVPP_EN1 AVPP_EN0 A5VDET/AGP1 AVCC3EN# AVCC5EN# B5VDET/BGP1 RESETDRV AREG# ACD3 ACD1# ACD4 ACD11 ACD5 ACD12 ACD6 ACD13 ACD7 ACD14 ACE1# ACD15 ACA10 ACE2# AOE# VCCSLOT#0 ACA11 ACIORD# VCC ACA9 ACIOWR# ACA8 GND ACA17 ACA13 ACA18 ACA14 ACA19 AWE#/PGM# ACA20 ARDY/BSY# ACA21 ACA16 ACA22 ACA15 ACA23 ACA12 ACA24 ACA7 ACA25 ACA6 ACA5 ARESET VCCSLOT#0
5
RF5C296/RF5C396L/RB5C396/RF5C396
PIN ASSIGNMENTS
* RF5C396L/RF5C396
Pin No. Symbol Pin No. Symbol Pin No. Symbol Pin No. Symbol
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
AVPP_EN1 AVPP_EN0 A5VDET/AGPI AVCC3EN# AVCC5EN# B5VDET/BGPI RESETDRV AREG# ACD3 ACD1# ACD4 ACD11 ACD5 ACD12 ACD6 ACD13 ACD7 ACD14 ACE1# ACD15 ACA10 ACE2# AOE# VCCSLOT#0 ACA11 ACIORD# VCC ACA9 ACIOWR# ACA8 GND ACA17 ACA13 ACA18 ACA14 ACA19
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
AWE#/PGM# ACA20 ARDY/BSY# ACA21 ACA16 ACA22 ACA15 ACA23 ACA12 ACA24 ACA7 ACA25 ACA6 ACA5 ARESET VCCSLOT#0 ACA4 AWAIT# ACA3 AINPACK# ACA2 ACA1 ABVD2/SPKR# ACA0 ABVD1/STSCHG# ACD0 ACD8 ACD1 ACD9 ACD2 ACD10 AWP/IOIS16# ACD2# GND BREG# BCD3
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
BCD1# BCD4 BCD11 BCD5 BCD12 BCD6 GND BCD13 BCD7 BCD14 BCE1# BCD15 BCA10 BCE2# BOE# VCCSLOT#1 BCA11 BCIORD# BCA9 BCIOWR# BCA8 BCA17 BCA13 BCA18 BCA14 BCA19 BWE#/PGM# BCA20 BRDY/BSY# BCA21 BCA16 BCA22 BCA15 BCA23 BCA12 BCA24
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
BCA7 BCA25 GND BCA6 BCA5 BRESET BCA4 BWAIT# VCCSLOT#1 BCA3 BINPACK# BCA2 BCA1 BBVD2/SPKR# BCA0 BBVD1/STSCHG# BCD0 BCD8 BCD1 BCD9 BCD2 BCD10 BWP/IOIS16# BCD2# RIOUT# SD15 SD14 SD13 SD12 VCCAT SD11 GND SD10 SD9 SD8 MEMW#
6
RF5C296/RF5C396L/RB5C396/RF5C396
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
MEMR# LA17 LA18 IRQ14 SA19 IRQ15 LA20 IRQ12 LA21 IRQ11 LA22 IRQ10 LA23 IOCS16# SBHE# MEMCS16#
161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
SA0 SA1 SYSCLK SA2 SA3 BALE SA4 SA5 SA6 IRQ3 SA7 IRQ4 SA8 IRQ5 SA9 SA10
177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192
IRQ7 SA11 SA12 REFRESH# SA13 SA14 SA15 SA16 IOR# IOW# AEN IOCHRDY SD0 SD1 ZEROWS# GND
193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
SD2 SD3 VCCAT SD4 SD5 IRQ9 SD6 SD7 POWERGOOD SPKROUT# INTR# BVPP_EN1 BVPP_EN0 BVCC3EN# BVCC5EN# CS#
*)
I : Active "low" signals are indicated by "#".
7
RF5C296/RF5C396L/RB5C396/RF5C396
PIN CONFIGURATION
* RB5C396
A
BC
DE
FG
HJ
K
L
MN
PR
T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 :GND
PIN ASSIGNMENTS
* RB5C396
Pin No. Symbol Pin No. Symbol Pin No. Symbol Pin No. Symbol
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
LA22 LA21 LA19 LA17 SD8 SD11 SD14 BCD2# BCD9 BCD0 BCA1 BCA3 BRESET BCA25 BCA23 BCA16
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16
IOCS16# IRQ11 IRQ12 IRQ14 MEMR# SD9 SD12 SD15 BCD2 BCD8 BBVD2/SPKR# BINPACK# BCA4 BCA6 BCA21 BRDY/BSY#
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16
SYSCLK SA2 SBHE# IRQ15 LA18 SD10 SD13 RIOUT# BWP/IOIS16# BCD1 BBVD1/STSCHG# BWAIT# BCA24 BCA12 BCA20 BCA14
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16
BALE SA5 MEMCS16# SA1 IRQ10 MEMW# GND VCCAT BCD10 BCA0 BCA2 BCA5 BCA7 BCA19 BCA18 BCA17
8
RF5C296/RF5C396L/RB5C396/RF5C396
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16
IRQ3 SA7 SA6 SA3 LA23 LA20 GND GND GND VCCSLOT#1 GND BCA15 BCA22 BCA13 BCA8 BCIORD# SA8 IRQ5 SA10 IRQ4 SA0 GND GND GND GND GND GND BWE# BCA9 BOE# BCA11 BCE2#
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16
IRQ7 SA11 SA12 SA9 SA4 GND GND GND GND GND GND GND BCIOWR# BCD15 BCD10 BCE1# REFRESH# SA13 SA15 SA14 GND GND GND GND GND GND GND GND VCCSLOT#1 BCD7 BCD14 BCD13
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16
SA16 IOW# IOR# GND GND GND GND GND GND GND GND GND GND BCD6 BCD12 BCD5 AEN SD0 IOCHRDY VCCAT GND GND GND GND GND GND GND GND ACD8 BCD11 BCD4 BCD1#
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16
SD1 SD2 ZEROWS# SD4 INTR# GND GND GND GND GND GND ACA2 AWP/IOIS16# BCD3 BREG# ACD2# SD3 SD5 SD6 CS# AVPP_EN1 AVCC5EN# ACD4 GND GND GND ACA7 ACA4 ABVD1/STSCHG# ACD9 ACD10 ACD2
9
RF5C296/RF5C396L/RB5C396/RF5C396
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16
IRQ9 SD7 SPKROUT# B5VDET/BGPI ACD3 ACD13 VCCSLOT#0 VCC GND ACA21 ARDY/BSY# VCCSLOT#0 ACA1 AINPACK# ACD1 ACD0
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16
POWERGOOD BVPP_EN1 A5VDET/AGPI AVCC3EN# ACD5 ACE1# ACE2# ACIORD# ACIOWR# ACA13 ACA19 ACA15 ACA24 ACA3 ACA0 ABVD2/SPKR#
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
BVPP_EN0 BVCC3EN# AREG# ACD11 ACD6 ACD14 ACA10 ACA11 ACA8 ACA18 AWE# ACA16 ACA23 ACA25 ACA5 AWAIT#
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
BVCC5EN# AVPP_EN0 RESETDRV ACD1# ACD12 ACD7 ACD15 AOE# ACA9 ACA17 ACA14 ACA20 ACA22 ACA12 ACA6 ARESET
10
RF5C296/RF5C396L/RB5C396/RF5C396
PIN DESCRIPTION
1. ISA Bus Interface
Symbol Function Pin No. RF5C296 RF5C396*1 I/O* Drive
LA23 to LA17 ISA Bus System Address 23 to 17
96,94,92,89,87,85, 157,155,153,151, 149,147,146 84 123,122,121,120, 118,117,115,114, 112,110,108,107, 106,104,103,101, 100 126 105 98 119 71,73,74,75,77,79, 80,81,140,139, 137,136,134,132, 130,129 124 125 83 82 97 99 131 184,183,182,181, 179,178,176,175, 173,171,169,168, 167,165,164,162, 161 187 166 159 180 134,135,136,137, 139,141,142,143, 200,199,197,196, 194,193,190,189 185 186 145 144 158 160 191
I
--
SA16 to SA0 ISA Bus System Address 16 to 0
I
--
AEN BALE SBHE# REFRESH#
Address Enable. High signal is input in DMA mode. Address Latch Enable. This signal latches LA23 pin to LA17 pin. System Bus High Byte Enable This active low signal indicates that an ISA-bus refresh cycle is either requested or in progress.
I I I I
-- -- -- --
SD15 to SD0 System Data Bus
I/O
12mA
IOR# IOW# MEMR# MEMW# IOCS16#
I/O Port Read I/O Port Write Memory Read Memory Write 16bit I/O Transfer Mode Chip Select
I I I I O(OD) O(OD) O(TS) O(TS)
-- -- -- -- 16mA 16mA 12mA 16mA
MEMCS16# 16bit Memory Transfer Mode Chip Select ZEROWS# IOCHRDY Zero Wait State I/O Channel Ready. This active High signal indicates that the accessed device on the ISA-bus is ready to terminate the bus cycle. Interrupt Request Signal. IRQ3, IRQ4, IRQ5, IRQ7, IRQ9, IRQ10, IRQ11, IRQ12, IRQ14, IRQ15. Level mode interrupt or Edge mode interrupt is programmable. IRQ12 can be used as a LED driver. IRQ9, IRQ10, IRQ11, or IRQ15 may be used as system side DACK#, system side DREQ, and system side TC respectively in DMA mode.
127
188
IRQn
109,111,113,116, 138,95,93,90,86, 88
170,172,174,177, 198,156,154,152, 148,150
O(TS)
8mA
*) *1)
I : Input, O : Output, I/O : Input/Output, O (OD) : Open Drain Output, O (TS) : Tri-State Output. Pin No. of the RB5C396 differ from those of others. Refer to "PIN CONFIGURATION".
11
RF5C296/RF5C396L/RB5C396/RF5C396
Symbol
Function
Pin No. RF5C296 RF5C396*1
I/O*
Drive
SYSCLK
System Clock Input Chip Select input. This signal is use for configuration CS# control power down mode, in case of driving by the I/O address.
102
163
I
--
CS#
7
208
I
--
*) I : Input, O : Output, I/O : Input/Output, O (OD) : Open Drain Output, O (TS) : Tri-State Output. *1) Pin No. of the RB5C396 differ from those of others. Refer to "PIN CONFIGURATION".
12
RF5C296/RF5C396L/RB5C396/RF5C396
2. Card Slot Interface
Symbol Function Pin No. RF5C296 RF5C396*2 I/O*1 Drive
CA25 to CA0
Card Address Output
48,46,44,42,40,38,36, 34,32,41,43,35,33,45, 27,24,29,31,47,49,50, 53,56,58,59,61
Slot#0 : 48,46,44,42,40,38,36, 34,32,41,43,35,33,45, 25,21,28,30,47,49,50, 53,55,57,58,60 Slot#1 : 110,108,106,104,102, 100,98,96,94,103,105, 97,95,107,89,85,91,93, 109,112,113,115,118, 120,121,123
O(TS)
8mA
CD15 to CD8
Card Data Bus High Byte. Input buffer is 23,21,17,14,12,68,66, disabled when card slot power supply is off 64 or card is not inserted.
Slot#0 : 20,18,16,14,12,67,65,63 Slot#1 : I/O(PD) 8mA 84,82,80,77,75,130, 128,126
CD7 to CD0
Slot#0 : Card Data Bus Low Byte. Input buffer is 17,15,13,11,9,66,64,62 I/O(PD) 8mA Slot#1 : disabled when card slot power supply is off 19,15,13,11,9,67,65,63 81,78,76,74,72,129, or card is not inserted. 127,125 Card Enable High Byte Card Enable Low Byte Card I/O Read Card I/O Write Card Output Enable Card Write Enable/Program The battery voltage detect input 1 on the memory PC card, and Card Status Change#/Ring indicate# input on the I/O card. The battery voltage detect input 2 on the memory PC card, and SPEAKER# (Digital Audio) input on the I/O card. This pin may also be used as card side DREQ in DMA mode. 25 22 28 30 26 37 Slot#0 : 22 Slot#1 : 86 Slot#0 : 19 Slot#1 : 83 Slot#0 : 26 Slot#1 : 90 Slot#0 : 29 Slot#1 : 92 Slot#0 : 23 Slot#1 : 87 Slot#0 : 37 Slot#1 : 99 Slot#0 : 61 Slot#1 : 124 O (TS) O (TS) O (TS) O (TS) O (TS) O (TS) 8mA 8mA 8mA 8mA 8mA 8mA
CE2# CE1# CIORD# CIOWR# OE# WE#/PGM# BVD1 (STSCHG# /RI#)
62
I
--
BVD2 (SPKR#)
60
Slot#0 : 59 Slot#1 : 122
I
--
*1) *2)
I : Input, O : Output, I/O : Input/Output, I/O (PD) : Input/Output with Pull-down Register, O (TS) : Tri-State Output. All card slot interface signal names are pretended with A-(slot#0) and B-(slot#1). For example, ACA25 to ACA0 are the card address buses to the slot#0. Pin No. of the RB5C396 differ from those of others. Refer to "PIN CONFIGURATION".
13
RF5C296/RF5C396L/RB5C396/RF5C396
Symbol
Function
Pin No. RF5C296 RF5C396*2
I/O*1
Drive
CD1#, CD2# RDY/BSY# (IREQ#)
Card Detect Input 1 & 2*3 READY/BUSY# input on the memory PC card, and IREQ# input on the I/O card. When this signal is "L" memory access is limited to Attribute memory. During normal access for I/O, this signal must be kept "L". During DMA cycle, this signal must be kept "H". This pin may also be used as card side DACK in DMA mode. Bus Cycle Wait Input from PC Card Write Protect switch input on the memory PC card and, IOIS16# is asserted by PC card when the I/O cycle is 16bit on the I/O. This pin may also be used as card side DREQ in DMA mode. Card Reset Output Input Acknowledge. "L" is output to INPACK# on the PCMCIA bus only when I/O ports accessed during I/O signal read are enabled on PC cards that support this signal. When INPACK# signal is enabled for RF5C296/RF5C396, I/O signal read data will be output to the system only when the INPACK# signal is enabled. This pin may also be used as card side DREQ in DMA mode.
10,70 39
Slot#0 : 10,69 Slot#1 : 73,132 Slot#0 : 39 Slot#1 : 101
I I
-- --
REG#
8
Slot#0 : 8 Slot#1 : 71
O(TS)
4mA
WAIT#
55
Slot#0 : 54 Slot#1 : 116
I
--
WP (IOIS16#)
69
Slot#0 : 68 Slot#1 : 131
I
--
RESET
51
Slot#0 : 51 Slot#1 : 114
O(TS)
4mA
INPACK#
16
Slot#0 : 56 Slot#1 : 119
I
--
*1) *2) *3)
I : Input, O : Output, I/O : Input/Output, O (TS) : Tri-State Output. All card slot interface signal names are pretended with A-(slot#0) and B-(slot#1). For example, ACA25 to ACA0 are the card address buses to the slot #0. Pin No. of the RB5C396 differ from those of others. Refer to "PIN CONFIGURATION". CD1# and CD2# are powered by VCC_AT instead of VCC_SLOT because hot plug-in/out is supported during card slot power is off.
14
RF5C296/RF5C396L/RB5C396/RF5C396
3. Other Control Pins
Symbol Function RF5C296 Pin No. RF5C396*2 I/O*1 Drive
POWERGOOD
POWERGOOD input. Connect to GND if not used. Reset Drive Input. This active High signal indicates Main System Cold Reset. Speaker Output. Passes through SPKR# from an I/O card. Ring Indicate Output. Passes through RI_OUT# from an I/O card. Interrupt Request Output 5V detect input/General Purpose Input, on GPI enable. IRQ generation is programmable when transition occurs. Basically user can use this input arbitrarily. This pin shall be connected to the VSI# in the card slot for use as 5V Detect Input. Power Control (5V) Power Control (3.3V) Program Power Supply Control 0 (VPP_VCC) Program Power Supply Control 1 (VPP_PGM)
141
201
I
--
RESETDRV
144
7
I (PD)
--
SPKROUT#
142
202
O (TS)*3
4mA
RI_OUT# INTR#
5 143
133 203
O (TS)*3 O (TS)*3
4mA 4mA
5VDET/GPI
4
Slot#0 : 3 Slot#1 : 6
I (PU)
--
VCC5EN# VCC3EN# VPP_EN0 VPP_EN1
1 6 2 3
Slot#0 : 5 Slot#1 : 207 Slot#0 : 4 Slot#1 : 206 Slot#0 : 2 Slot#1 : 205 Slot#0 : 1 Slot#1 : 204
O O O O
4mA 4mA 4mA 4mA
*1) *2) *3)
I : Input, O : Output, I/O : Input/Output, I (PU) : Input with Pull-up Register, I (PD) : Input with Pull-down Register, O (TS) : Tri-State Output. All card slot interface signal names are pretended with A-(slot#0) and B-(slot#1). For example, ACA25 to ACA0 are the card address buses to the slot #0. Pin No. of the RB5C396 differ from those of others. Refer to "PIN CONFIGURATION". Applicable to only RF5C296.
15
RF5C296/RF5C396L/RB5C396/RF5C396
4. Power and Ground Supply Pins
Symbol Function Pin No. RF5C296 RF5C396*1
VCC VCCAT VCCSLOT GND
VCC for Core Logic VCC for ISA Interface Signals VCC for Card Interface Signals Ground Pin
91 76, 135 18, 52 20,54,57,72,78, 128,133
27 138, 195 Slot#0 : 24,52 Slot#1 : 88,117 31,70,79,111,140, 192
*1)
All card slot interface signal names are pretended with A-(slot#0) and B-(slot#1). For example, ACA25 to ACA0 are the card address buses to the slot#0. Pin No. of the RB5C396 differ from those of others. Refer to "PIN CONFIGURATION".
16
RF5C296/RF5C396L/RB5C396/RF5C396
BLOCK DIAGRAM
Slot#1(RF5C396) Slot#0 CA11 to CA0 SD15-SD0 AEN REFRESH# LA23-LA17 SA16-SA0 CS# BALE ISA BUS CONTROL LOGIC CD15 to CD8 DATA BUS BUFFER CD7 to CD0 ADDRESS MAPPING LOGIC ADDRESS BUFFER CA25 to CA12
SBHE IOR#,IOW# MEMR#, MEMW# IOCS16# MEMCS16# ZEROWS#, IOCHRDY IRQn(DREQ, DACK#,TC) SYSCLK
CE1#, CE2# CARD STROBES CIORD#, CIOWR# OE#, WE#(TC#) REG#(DACK#)
POWERGOOD RESETDRV
POWER CONTROL
VPP_EN0 VPP_EN1 VCC5EN# VCC3EN# BVD1 (STSCHG#,RI#) BVD2(SPKR#,DREQ) CD1#,CD2# RDY/BSY#(IREQ#) WAIT# WP(IOIS16#,DREQ) RESET INPACK#(DREQ)
SPKROUT# RI_OUT INTR#
MISC. CONTROL
SOCKET CONTROL AND STATUS
5VDET/GPI
17
RF5C296/RF5C396L/RB5C396/RF5C396
FUNCTIONAL DESCRIPTION
RF5C296 (RF5C396) is a controller for supporting one (two) card slot compliant to PCMCIA2.1/JEIDA4.2 68pin standard. Direct connection to the card slot is allowed due to the complete buffering of signals to the card. RF5C296/RF5C396 can also interface directly to the ISA bus.
1. Address Mapping
Each socket has five independently enabled and controlled system memory address mapping windows and two independently enabled and controlled system I/O address mapping windows. Some portions of 64MB common memory and 64MB attribute memory spaces on the PC Cards can be mapped into the smaller 16MB ISA address space. Mapping of each system memory window can start and stop on any 4kB boundary of ISA system memory above 64kB except for I/O address space of 0000h to 0FFFFh by setting the system memory mapping start register, system memory mapping stop register, and card memory offset register. The summation result (in 2's complement) of the value in the card memory offset register and ISA system address value will result in the memory card address. Each window has independent control of data bus size, the number of wait cycles, and the selection of common memory area or attribute memory area.
PCMCIA Socket Memory Address Space
3FF FFFFh=64MB
ISA Memory Address Space
System Memory Window: Memory Map End Address D000:FFFFh Memory Map Start Address D000:0000h Mapping
Resulting PCMCIA Socket Memory Window:
End Address 000 FFFFh Start Address 000 0000h
Memory Map Address Offset=3F30XXXh = -00D0000h(two's complement when negative offset)
Each I/O window can be mapped with 1byte resolution between 0000h to 0FFFFh in the ISA system address space by setting the I/O start address register and the I/O stop address register. I/O mapping is not allowed during the DMA cycle.
18
RF5C296/RF5C396L/RB5C396/RF5C396
2. Power Management
When card slot is empty or the power supply is off, each card slot has independently power management because each slot has its own buffers and transceivers. In order to achieve the low power consumption especially for the notebook PCs, each address mapping circuit will be powered down when it is not activated. In addition to the function, setting the power down bit in the global control register to "1" enables the RF5C296/RF5C396 to go into the power down mode. There is a single power down control bit which can be written with either a Slot#0 or Slot#1 Global Control Register Index. Setting this bit to "1" goes into the power down mode. Even in the power down mode, RF5C296/RF5C396 can generate a card status change interrupt and PC Card interrupt for I/O cards. The RF5C296/RF5C396 can also generate the RI_OUT# signal when configured for ring indicate resume from I/O cards. In this Power down mode, the following ISA bus signals will be ignored. SD[15 : 0], LA[23 : 17], SA[16 : 0], IORD#, IOWR#, AEN, BALE, SYSCLK, MEMW#, MEMR#, SBHE#
3. Mixed Voltage Operation
There are three/four different power nets ; VCC for ISA bus interface, VCC for core logic, VCC for card slot interface ; to be handled in RF5C296/RF5C396. Each of these power nets can be independently running at 3.3V or 5V. All of the voltage combinations listed on the next page are supported. RF5C296/RF5C396 can operate even with the single power supply of 5V or 3.3V
VCC_AT ISA bus
VCC_CORE
VCC_SLOT#0 Slot#0
Slot#0 Interface ISA bus Interface Core Logic Slot#1 Interface
RF5C296/RF5C396
Slot#1
VCC_SLOT#1
19
RF5C296/RF5C396L/RB5C396/RF5C396
Core (VCC_CORE)
Card Slot#0 (VCC_SLOT#0)
Card Slot#1 (VCC_SLOT#1)
ISA bus Interface (VCC_AT)
5V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
5V 5V 3.3V 5V 3.3V 5V 5V 3.3V 3.3V
5V 5V 5V 3.3V 3.3V 5V 3.3V 5V 3.3V
5V 5V 5V 5V 5V 3.3V 3.3V 3.3V 3.3V
Mixed Voltage Operation
When 5VDET/GPI pin is connected to PCMCIA card slot pin #43 (VS1#) as shown in the figure, the following should be considered. (1) Interface Status Register bit7*1 indicate inverted 5VDET/GPI. (2) Card Detect and Control Register bit2*1 (GPI enable) must be kept "0".
Power Control Circuits VCC3EN# VCC5EN#
*2
PCMCIA Card Slot
VCCSLOT# 5VDET/GPI RF5C296/RF5C396
VCC
*2
VS1#
*1) *2)
Refer to page 27 "INTERNAL RESISTERS" As shown in the above table, the RF5C296 and the RF5C396 allow sharing of a power supply between their VCC_SLOTs and the PCcard slots, provided that the VCC_CORE should be set to 3.3V.
20
RF5C296/RF5C396L/RB5C396/RF5C396
4. Address Mapping
To prevent any conflict between interrupt request signals derived from the RF5C296 or the RF5C396 and from any other device, the PC card status change, such as fluctuations in the voltage of the battery for the PC card and insertion or removal of the PC card into or from the PC card slot, as well as interrupt request signals (IREQ#) derived from the I/O cards can be assigned to one of the ten interrupt lines for ten interrupt request signals (IRQ15, IRQ14, IRQ12, IRQ11, IRQ10, IRQ9, IRQ7, IRQ5, IRQ4, and IRQ3). These interrupt requests are programmable to the level mode or the edge trigger mode. In addition to steering IRQn output, INTR# output is also used as an interrupt output. The INTR# pin signal is normally input to the EXTSMI# pin of the Intel 386SL to output a low-level pulse having three times the width of the SYSCLK pulse at the time of interrupt request generation and a high-level pulse at any other time. In addition to these interrupts sources, it is programmable that IRQs will be generated when the transition occurs on GPI (General Purpose Input). If card status change while other card status change interrupt request, second interrupt request pulse is not generated. In this case, the appropriate bit must be set to "1" in the Card Status Change Register (Index : 04h) in the Explicit Write Back Acknowledge Mode to enable interrupt request recognition by the host system interrupt processing routine. Upon interrupt request recognition, the bit is reset to "0". Incidentally, all the bits in the Card Status Change Register (Index : 04h) are reset to "0" when it is read in any other mode than the Explicit Write Back Acknowledge Mode. IRQ9, IRQ10, IRQ12, IRQ11 (or IRQ15) are multi-function pins. In PCMCIA-ATA mode, IRQ12 can drive LED. In DMA mode, IRQ9, IRQ10, IRQ11 (or IRQ15) work as DACK#, DREQ, TC.
5. Bus Sizing
In addition to 16bit bus cycle, RF5C296/RF5C396 supports 8bit bus cycle. The 8bit bus cycle to a PC Card can be generated even when the window is configured for 16bit. This means that the combination of SBHE# input and SA0 input override the data size configuration. On 8bit host systems, the SBHE# input must be pulled high (inactive) for proper operation. The following is a truth table of the card enable logic.
16bit Window SBHE# A0 CE2# CE1#
YES YES YES YES NO NO NO NO
L L H H L L H H
L H L H L H L H
L L H H H H H H
L H L L L L L L
21
RF5C296/RF5C396L/RB5C396/RF5C396
6. Internal Register Access
All of the control registers of the RF5C296/RF5C396 are 8bit width registers and can be accessed using an indirect indexing scheme. Only two I/O addresses such as (3E1h) and (3E0h) are used to access all control registers. RF5C296/RF5C396 has the external decode mode. In this mode, I/O address is decoded outside and input to CS#. When RESETDRV falls, if the level of INTR# pin is "H" ("L"), internal decode mode (external decode mode) can be selected. Consequently, these operations can be enabled by externally pulling up or down the INTR# pin to such a degree as not to affect normal operation. In the Internal Decode Mode, too, the CS# pin should be caused to transition to low level at the time of internal register access (the CS# pin should be caused to transition to high level only in the Power Down Mode). The Index Register has the bit settings shown below :
Index Register (3E0h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
"0": Device#0 "1": Device#1
"0": Slot#0 "1": Slot#1
Register Index
There are 56 control registers provided for each PC card slot. The Index Register has bit7 for indicating a device number depending on the status of the SPKROUT# pin for the RF5C396 or the RI_OUT# pin for the RF5C296 at the falling edge of the RESETDRV pin signal. For the RF5C296, in particular, the Index Register has bit6 (Slot bit) for indicating a device number depending on the status of the SPKROUT# pin at the falling edge of the RESETDRV pin signal. Both the SPKROUT# and RI_OUT# pins operate in the same manner as the INTR# pin described above. The status of the SPKROUT# pin (for the RF5C396) or the RI_OUT# pin (for the RF5C296) corresponds to the index range as shown in the tables in "7. Plural (Three) Slot Systems" on the next page. Note that these pins also require their status control for connecting a single unit of the RF5C296 or the RF5C396.
22
RF5C296/RF5C396L/RB5C396/RF5C396
7. Plural Slots System
7.1 Up to 4 slots
As described before, the settings of bit7 and bit6 (Slot bit) in the Index Register depend on the status of the SPKROUT# pin for the RF5C396 or the RI_OUT# pin for the RF5C296 and on the status of the the SPKROUT# pin for the RF5C296, respectively, at the falling edge of the RESETDRV pin signal. Therefore, 4 slots system can be constructed using plural RF5C296/RF5C396's without modifying I/O address (3E0h, 3E1h) 1-slot system : one RF5C296 2-slot system : one RF5C396 or two RF5C296 3-slot system : one RF5C396 and one RF5C296, or three RF5C296 4-slot system : two RF5C396, or one RF5C396 and two RF5C296, or four RF5C296 The following tables show the relation between the index range and the status of SPKROUT# and RI-OUT# when RESETDRV falls. * RF5C296
RI_OUT# SPKROUT# Device bit Slot bit Index Range
VDD VDD GND GND
VDD GND VDD GND
0 0 1 1
0 1 0 1
00 to 3Fh 40 to 7Fh 80 to BFh C0 to EFh
* RF5C396
SPKROUT# Device bit Slot bit Index Range
VDD VDD GND GND
0 0 1 1 Notice
0 1 0 1
00 to 3Fh 40 to 7Fh 80 to BFh C0 to EFh
Access to any other index range than is specified at power-on is invalidated while any attempt to read the Index Register results in a data bus output of high impedance.
7.2 Five or More Slots
More than five PC card slots can also be supported through external decoding of the A15 to A1 pin signals for input to the CS# pin and thereby setting of any given I/O addresses of the internal registers for the RF5C296 and the RF5C396.
23
RF5C296/RF5C396L/RB5C396/RF5C396
8. PCMCIA-ATA Mode
RF5C296/RF5C396 supports a PCMCIA-ATA interface mode. The following table shows the card interface signals when PCMCIA-ATA mode is configured.
PIN No. PCMCIA I/O Interface Signal ATA Interface Signal PIN No. PCMCIA I/O Interface Signal ATA Interface Signal
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
GND CD3 CD4 CD5 CD6 CD7 CE1# CA10 OE# CA11 CA9 CA8 CA13 CA14 WE# IREQ# VCC VPP1 CA16 CA15 CA12 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 CD0 CD1 CD2 IOIS16# GND
GND CD3 CD4 CD5 CD6 CD7 CE1# CA10 OE# CA11 CA9 CA8 CA13 CA14 WE# IREQ#(IREQ) VCC VPP1 CA16 CA15 CA12 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 CD0 CD1 CD2 IOIS16# GND
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
GND CD1# CD11 CD12 CD13 CD14 CD15 CE2# NC CIORD# CIOWR# CA17 CA18 CA19 CA20 CA21 VCC VPP2 CA22 CA23 CA24 CA25 RFU RESET WAIT# NC REG# SPKR# STSCHG# CD8 CD9 CD10 CD2# GND
GND CD1# CD11 CD12 CD13 CD14 CD15 CE2# NC CIORD# CIOWR# CA17 CA18 CA19 CA20 * VCC VPP2 * * * * NC RESET WAIT# NC REG# LED# STSCHG# CD8 CD9 CD10 CD2# GND
*)
The signals are settable in the internal registers of RF5C296/RF5C396.
24
RF5C296/RF5C396L/RB5C396/RF5C396
Setting the bit0 of the Mode Control Register 1 (Index=1Fh) to "1" configures the corresponding card slot to the PCMCIA-ATA mode. In PCMCIA-ATA mode, if the bit1 of the Mode Control Register is set to "1", the SPKR# input works as an LED input and IRQ12 works as an open drain LED output. At this time SPKROUT# will become inactive. Bits2 to 6 can be set to specify the values of the CA21 to CA25 pin signals (marked with "*" in the pin definition table in the PCMCIA-ATA Mode on the previous page). In the PCMCIA-ATA Mode, the output CA21 to CA25 pin signals assume the values thus specified by bits2 to 6. Bit7 can be set to prevent any conflict between the system floppy disk signal and the card interface signals. When set to "1", bit7 is disabled during reading from an I/O address of 3F7h and 377h on the system data bus.
Mode Control Register 1 (Index=1Fh) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
377h, 3F7h Disable (in I/O Read)
A25
A24
A23
A22
A21
LED Enable
PCMCIAATA Mode
9. DMA Mode
RF5C296/RF5C396 provide the DMA Mode for supporting interfacing with external floppy disk units or other DMA devices via the PC card slots. Setting bit1 of Mode Control Register 3 to "1" enables DMA mode. The DMA data will be transferred to/from DMA capable PC Card with the ISA bus as a DMA master. On the DMA mode, some of RF5C296/RF5C396 signal pins will be redefined. IRQ9 will work as DACK# input, IRQ10 will work as DREQ output, IRQ11 (or IRQ15) will work as TC input. DREQ from the PC Card can be assigned to one of three PCMCIA inputs (IOIS16#, SPKR# or INPACK#) by setting bit7 and bit6 of Mode Control Register 2.
ISA bus DREQ DACK# TC IRQ 10 IRQ 9 IRQ 11(or15) IOIS 16# SPKR# or INPACK# REG# DREQ DACK# IOIS 16# , SPKR#, or INPACK# REG# PC card
RF5C296/FR5C396
DMA made configuration
DMA transfer between the ISA system memory and the I/O card is available in the following two types : 1) DMA transfer between the ISA system memory and the I/O card 2) DMA transfer between memory in the I/O card and the I/O port via the system data bus.
Notice
Only one slot at a time should be enabled for DMA transfer. And DMA transfer to/from DMA capable PC Card may be 8 or 16bit as shown in the bus sizing table of page 21.
25
RF5C296/RF5C396L/RB5C396/RF5C396
The TC# (terminal count) pin signal input to the PC card becomes active low for output from the OE# pin at a cycle for reading from the PC card (a cycle for writing to the memory) and from the E# pin at a cycle for writing to the PC card (a cycle for reading from the memory). Further, the output REG# pin signal is always held at high level during DMA transfer. Thus, it is easy to distinguish between DMA transfer and ordinary bus cycles. Namely, the REG# pin signal functions as DMA transfer acknowledgment for the PC card.
Notice on the DMA mode
1) IRQ9, IRQ10 and IRQ11 (or IRQ15) are redefined as DMA signals for ISA Bus. Therefore these signals can not be used as interrupt lines. 2) Bit5 of General Control Register must be set to "1" to select I/O card. 3) If WP/IOIS16# is used as DREQ, bit4 of Interface Status Register indicates DREQ from PC Card. 4) If BVD2/SPKR# is used as DREQ, SPKROUT# and LED output can not be used. 5) If INPACK# is used as DREQ, bit2 of Mode Control Register 2 must be kept "0". 6) TC input can be assigned to one of two IRQ signals (IRQ11 or IRQ15) by setting bit4 of Mode Control Register .
26
RF5C296/RF5C396L/RB5C396/RF5C396
INTERNAL REGISTERS
RF5C396 has the registers both for Slot#0 (2) and Slot#1 (3). RF5C296 has the registers only for Slot#0 (1, 2, 3). The internal registers have default bit settings (immediately after the falling edge of the RESETDRV pin signal when the POWERGOOD pin signal is set to "0") as enumerated below:
1. Chip Control
1.1 Identification and Revision Register*
Index : 00h Default value : 1000 0011b Read only bit7 to bit6 : These bits indicate the type of PC Cards supported by the RF5C296/RF5C396.
bit7 bit6 Interface
0 0 1 1
0 1 0 1
I/O Only Memory Only Memory & I/O Reserved
bit5 : Reserved bit4 : Reserved bit3 : Revision# : 0 bit2 : Revision# : 0 bit1 : Revision# : 1 bit0 : Revision# : 1
*)
In this register, bits7 and 6 identify the type of the PC card controllers while bits3 to 0 indicate revision numbers. If this register is read, can be read back "83h".
1.2 Interface Status Register
Index : 01h bit7 bit6 bit5 Default value : Depends on PC card slot status Read only : Indicates the state of the reverse of the GPI pin. : PC Card Power Active. Indicates the current power status of the socket. "0" shows that power to the socket is off, and "1" shows that the power is provided to the socket. : Ready/Busy Status Bit. This bit indicates the busy status when set to "0" and the ready status when set to"1" when the PC card is the memory card. Further, this bit specifies reading back of the IREQ# pin signal when the PC card is the I/O card. bit4 : Memory Write Protect. Indicates the state of the WP pin. Memory write accesses to the slot will not be blocked unless the Write Protect bit in the Card Memory Offset Address Register High Byte is set to "1".
27
RF5C296/RF5C396L/RB5C396/RF5C396
bit3
: Card Detect 2. This bit specifies reading back of the input CD2# pin signal in the inverted state. This bit will be set to "1" in the presence of the card in the slot when the IC core is connected to the external pullup resistor because the CD2# pin is connected to the GND pin inside the card.
bit2
: Card Detect 1. This bit specifies reading back of the input CD1# pin signal in the inverted state. This bit will be set to "1" in the presence of the card in the slot when the IC core is connected to the external pullup resistor because the CD1# pin is connected to the GND pin inside the card.
bit1 to 0 : Battery Voltage Detect 2&1. Bits 1 and 0 can be used to specify reading back of the status of the input BVD2 and BVD1 pin signals, respectively, when the PC card is the memory card. Bits 1 and 0 can also be used to specify the battery status as shown in the table below:
bit0 bit1 Status
0 0 1 1
0 1 0 1
Battery Dead Battery Dead Warning Battery Good
For I/O card, bit0 indicates the current status of the (STSCHG#/RI#) signal from the I/O card when the ring indicate enable bit in the Interrupt and General Control Register is set to "0".
1.3 Power and RESETDRV Control Register
Index : 02h bit7 Default value : 0000 0000b Read & Write
: Output Enable. When set to "0", this bit specifies high impedance for slot output signals from the following pins : CA [25 : 0], CD [15 : 0], CE1#, CE2#, CIORD#, CIOWR#, OE#, REG#, RESET, and WE#. Note that the pull-down resistor and input slot signal of the DC [15 : 0] pin remain valid.
bit6
: Disable Resume RESETDRV. If bit is set to "1" and PWRGOOD="1", the restable registers of RF5C296/RF5C396 will not be reset. If the RESETDRV is a result of a system reset (PWRGOOD= "0"), the reset able registers of RF5C296/RF5C396 will be reset regardless of the setting bit.
bit5
: Auto Power Switch Enable. When this bit is set to "1", the power control values specified by bits4 to 0 (Power Control Bits) in this register and bit0 in the Mixed Voltage Control Register (Index : 2Fh) are automatically output upon setting of both the CD1# and CD2# pin signals to "0". Conversely, upon setting of either the CD1# or CD2# pin signal to "1", all the the power control values become inactive. When this bit is set to "0", the power control values specified by bits4 to 0 (Power Control Bits) in this register and bit0 in the Mixed Voltage Control Register (Index : 2Fh) are output regardless of whether the CD1# and CD2# pin signals are set to "0" or "1".
28
RF5C296/RF5C396L/RB5C396/RF5C396
bit4 to bit0 : Power Control Bits. These bits cooperate with bit0 in the Mode Control Register (Index : 2Fh) to set the VCC3EN, VCC5EN, VPP_EN1, and VPP_EN0 pin signals to "0" or "1" as shown in the table below :
bit4 bit3*1 bit2*1 bit1 bit0 bit0 of Mode Control Register VCC3EN# VCC5EN# VPP_EN1*2 VPP_EN0*3
1 1 1 1 1 1 1 1 0

0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0 1
0 0 0 0 1 1 1 1 1
0 0 1 1 0 0 1 1 0
*1) *2)
bit3 and bit2 : don't care. VCCnEN# means VCC5EN# or VCC3EN#, this signal defined by voltage selection. The settings of bits 3 and 2 are don't care. The settings of the VPP_EN1 and VPP_EN0 pin signals to "0" and "0", "0" and "1", "1" and "0", and "1" and "1" specify their connection to no pin, connection to the VCC pin, connection to the VPP pin, and reservation, respectively.
1.4 Card Status Change Register
Index : 04h bit7tobit5 : Reserved bit4 : GPI Change Bit. This bit will be set upon generation of any interrupt due to the GPI pin status change. This bit is held at "0" unless the GPI Enable Bit is set to "1" in the Card Detect and General Control Register. bit3 bit2 bit1 : Card Detect Change. Bit is set to "1" when a change has been detected on either the CD#1 or CD2# pin. : Ready Change. Bit is set to "1" when a low to high has been detected on the Ready/Busy# pin. Bit reads "0" for I/O cards. : Bit is set to "1" when Battery Warning Condition has been detected. For the Battery Warning Condition, see the description of bits1 and 0 in the Interface Status Register (Index : 01h). Bit reads "0" for I/O cards. bit0 : Bit is set to "1" when Battery Dead Condition has been detected for memory card. For the Battery Warning Condition, see the description of bits1 and 0 in the Interface Status Register (Index : 01h). For I/O cards, bit is set to "1" if Ring Indicate Enable bit in the Interrupt and General Control Register is set to "0" and STSCHG#/RI# signal from I/O card has been pulled low. This bit reads "0" for I/O cards if the Ring Indicate Enable bit in the Interrupt and General Control Register is set to "1". Default value : 0000 0000h Read & Write
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RF5C296/RF5C396L/RB5C396/RF5C396
The Card Status Change Register contains the status for sources of the card status change interrupt. These sources can be enabled to generate a card status change interrupt by setting the corresponding bit in the Card Status Change Interrupt Configuration Register. There are two ways to reset this register, (1) Read Card Status Change Register (2) Write back "1" into the corresponding bit in the Card Status Change Register after setting Explicit Write Back Card Status Change Acknowledge bit to "1" in the Global Control Register.
1.5 Card Detect and General Control Register
Index : 16h Default value : 0000 0000b Read & Write
bit7 to bit6 : Reserved bit5 : Software Card Detect Interrupt. If the Card Detect Enable bit is set to "1" in the Card Status Change Interrupt Configuration Register, then writing "1" to the Software Card Detect bit in the Card Detect and General Control Register will cause a card detect and status change interrupt. The functionality and acknowledgement of this software interrupt will work the same way as the hardware generated interrupt. This bit is always read as "0". bit4 : Card Detect Resume Enable. When this bit is set to "1", and once a card detect change has been detected on the CD1# and CD2# inputs, RI-OUT# output will go "High" to "Low" and bit3 of Card Status Change Register will be set to "1". The RI_OUT# pin signal is held at "0" until bit3 is reset to "0" in the and Status Change Register. The RI_OUT# pin signal is not generated up on and detection unless the card detection enable bit is first set to "1" in the Card Status Interrupt Configuration Register (Index : 05h). If the card status change is routed to either the INTR# and any of IRQn signals, the setting of this bit to "1" will prevent INTR# and IRQn signal becoming active as a result of card status change. bit3 : GPI Transition Control. Default value is "0". If this bit is set to "0", a card status change interrupt will be generated when GPI# input goes "H" to "L". If this bit is set to "1", a card status change interrupt will be generated when GPI# input goes "L" to "H". bit2 bit1 : GPI Enable. If this bit is set to "1", a card status change interrupt will be generated when GPI# input changes. : Configuration Reset Enable. If this bit is set to "1", a reset pulse will be generated when both CD1# and CD2# goes "L" to "H". This reset pulse reset the following registers.
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RF5C296/RF5C396L/RB5C396/RF5C396
Interrupt and General Control (Index : 03h) (except INTR# enable bit) Address Window Enable (Index : 06h) (except MEMCS16# Decode A23 to A12 bit) I/O Control (Index : 07h) I/O Address n Start Low Byte (Index : 08h, 0Ch) I/O Address n Start High Byte (Index : 09h, 0Dh) I/O Address n Stop Low Byte (Index : 0Ah, 0Eh) I/O Address n Stop High Byte (Index : 0Bh, 0Fh) System Memory Address n Mapping Start Low Byte (Index : 10h, 18h, 20h, 28h, 30h) System Memory Address n Mapping Start High Byte (Index : 11h, 19h, 21h, 29h, 31h) System Memory Address n Mapping Stop Low Byte (Index : 12h, 1Ah, 22h, 2Ah, 32h) System Memory Address n Mapping Stop High Byte (Index : 13h, 1Bh, 23h, 2Bh, 33h) Card Memory Offset Address n Low Byte (Index : 14h,1Ch, 24h, 2Ch, 34h) Card Memory Offset Address n High Byte (Index : 15h,1Dh, 25h, 2Dh, 35h) bit0 : 16bit memory delay inhibit. Default value is "0". If this bit is set to "0", the falling edge of the control strobes OE# and WE# will be generated from the first falling edge of SYSCLK after the falling edge of MEMW# or MEMR# in the 16bit memory cycle. If this bit is set to "1", the control strobes OE# and WE# will not be synchronously delayed by SYSCLK.
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RF5C296/RF5C396L/RB5C396/RF5C396
1.6 Global Control Register
Index : 1Eh Default value : 0000b Read &Write
This register is not duplicated per slot. This register can be accessed from either Slot#0 or Slot1# in RF5C396. Consequently, access to indexes of 1Eh and 5Eh means access to the same register. bit7 to bit4 : Reserved bit3 bit2 : IRQ14 Pulse Mode Enable. Setting this bit to "1" and bit 1 (Level Mode Interrupt Enable) to "0" will enable the RF5C296/RF5C396 to support pulse-mode IRQ14 interrupt output. : Explicit Write Back Card Status Change Acknowledge Bit. Setting this bit to "1" will require an explicit write of "1" to the Card Status Change Register Bit which indicates an interrupting condition. Default value is "0". When this bit is set to "0", the card status change interrupt is acknowledged by reading the Card Status Change Register, and the register bits are cleared upon a read. bit1 : In the Level Mode, the IRQn pin signals are held at high impedance until generation of any interrupt caused by the Card Status Change Register (Index : 04h) or routed by the IRQn pin signals from the I/O card. When this bit is set to "1", the IRQn pin signals are caused to transition from high impedance to "0" upon interrupt generation and reverted to high impedance upon completion of interrupt processing (in the Level Mode). When this bit is set to "0", the IRQn pin signals are caused to transition from "1" to "0" upon interrupt enabling and from "0" to "1" upon interrupt generation, and becomes inactive upon completion of interrupt processing (in the Edge Mode). bit0 : Power Down Bit If this bit is set to "1", then setting CS# to "1" will go into the power down mode. During CS# controlled power down, all internal registers are inaccessible, outputs are disabled, and the chip is at minimum power consumption level. IRQn and RI_OUT# will still be active to monitor the card detect and RI# status for resume indication.
CS# Power Down Control Bit Power Down Mode
0 1 0 1
0 0 1 1
No No No Yes
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RF5C296/RF5C396L/RB5C396/RF5C396
1.7 Address Window Enable Register
Index : 06h Default value : 0000 0000b Read & Write
bit7 : I/O Window 1 Enable. If this bit is set to "0", an I/O access within the I/O address Window 1 will inhibit the card enable signal. bit6 : I/O Window 0 Enable. If this bit is set to "0", an I/O access within the I/O address Window 0 will inhibit the card enable signal. bit5 : MEMCS16# Decode A23 to A12. If this bit is set to "0", MEMCS16# is generated from a decode of A23 to A17. If this bit is set to "1", MEMCS16# is generated from a decode of A23 to A12. The MEMCS16# pin signal is output within any specified address range whether the PC card is the memory card or the I/O card. bit4 : Memory Window 4 Enable Bit. If this Bit is set to "0", a memory access within the Memory Window 4 will inhibit the card enable signal. bit3 : Memory Window 3 Enable Bit. If this Bit is set to "0", a memory access within the Memory Window 3 will inhibit the card enable signal. bit2 : Memory Window 2 Enable Bit. If this Bit is set to "0", a memory access within the Memory Window 2 will inhibit the card enable signal. bit1 : Memory Window 1 Enable Bit. If this Bit is set to "0", a memory access within the Memory Window 1 will inhibit the card enable signal. bit0 : Memory Window 0 Enable Bit. If this Bit is set to "0", a memory access within the Memory Window 0 will inhibit the card enable signal.
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RF5C296/RF5C396L/RB5C396/RF5C396
1.8 Interrupt and General Control Register
Index : 03h bit7 Default value : 0000 0000b : Ring Indicate Enable. Setting this bit to "0" for I/O card, the STSCHG#/RI# signal from the I/O card is used as the status change signal STSCHG#. The current status of the signal is then available to the read from the Interface Status Register and this signal can be configured as a source for the card status change interrupt. Setting this bit to "1", STSCHG#/RI# signal from the I/O card is used as a ring indicator signal and is passed through to the RI_OUT# pin. For memory PC Card, bit has no function. bit6 bit5 bit4 : PC Card Reset#. Setting this bit to "0" activates the Reset signal to the PC Card. The Reset signal will be active until this bit is set to "1". : PC Card type. Setting this bit to "1" selects an I/O card. Setting this bit to "0" selects a memory card. : INTR# Enable. Setting bit to "1" enables the card status change interrupt on the INTR# signal. If this bit is set to "0", the card status change interrupt is steered to one of the IRQn lines according bits7 through 4 in the card status change interrupt configuration register. bit3 to bit0 : IRQn level selection (I/O card only).
bit3 bit2 bit1 bit0 IRQn Selection
Read & Write
0 0 0 0 0 1 1 1 1 1 1
0 0 1 1 1 0 0 0 1 1 1
0 1 0 0 1 0 1 1 0 1 1
0 1 0 1 1 1 0 1 0 0 1
IRQ not Selected IRQ3 Enabled IRQ4 Enabled IRQ5 Enabled IRQ7 Enabled IRQ9 Enabled IRQ10 Enabled IRQ11 Enabled IRQ12 Enabled IRQ14 Enabled IRQ15 Enabled
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RF5C296/RF5C396L/RB5C396/RF5C396
1.9 Card Status Interrupt Configuration Register
Index : 05h Default value : 0000 0000b Read & Write
bit7 to bit4 : These bits select the redirection of the card status change interrupt if the interrupt is not selected to INTR# pin.
INTR# Enable bit bit3 bit2 bit1 bit0 IRQn Selection
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 1 1 1 1 1 1
0 0 1 1 1 0 0 0 1 1 1
0 1 0 0 1 0 1 1 0 1 1
0 1 0 1 1 1 0 1 0 0 1
IRQ not Selected IRQ3 Enabled IRQ4 Enabled IRQ5 Enabled IRQ7 Enabled IRQ9 Enabled IRQ10 Enabled IRQ11 Enabled IRQ12 Enabled IRQ14 Enabled IRQ15 Enabled redirected to INTR#

bit3 bit2
: Card Detect Enable. Setting bit to "1" enables a card status change interrupt when a change has been detected on CD1# or CD2# signals. : Ready Enable. Setting this bit to "1" enables a card status change interrupt when a "L" to "H" transition has been detected on READY/BUSY# signals. This bit is ignored when interface is configured for I/O card.
bit1 bit0
: Battery Warning Enable. Setting this bit to "1" enables a card status change interrupt when battery warning condition has been detected. This bit is ignored when interface is configured for I/O card. : Battery Dead Enable. For memory cards, Setting this bit to "1" enables a card status change interrupt when a battery dead condition has been detected. For I/O cards, a card status change interrupt will be generated if the STSCHG#/RI# has been pulled "L" assuming Ring Indicate Enable Bit (bit7) in Interrupt and General Control Register is set to "0".
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RF5C296/RF5C396L/RB5C396/RF5C396
2. I/O Mapping
2.1 I/O Control Register
Index : 07h Default value : 0000 0000b Read & Write
bit7 : I/O Window 1 Waite State. If this bit is set to "1" or this wait state is set by the wait# signal which is common to 8 and 16bit, 16bit system accesses occur with 1 additional wait state(4 SYSCLK). bit6 : I/O Window 1 Zero Waite State. If this bit is set to "1", 8bit system I/O accesses occur with zero additional wait states and ZEROWS# signal will be active. bit5 : I/O Window 1 IOCS16# Source. If this bit is set to "0", IOCS16# signal will be generated based on the value of the data size bit. If this bit is set to "1", IOCS16# signal will be generated based on the IOIS16# signal. bit4 : I/O Window 1 data size. "0" indicates 8bit mode, and "1" indicates 16bit mode. bit3 : I/O Window 0 Wait State. If this bit is set to "1" or this wait state is set by the wait # signal which is common to 8 and 16bit, 16bit system accesses occur with 1 additional wait state(4 SYSCLK). bit2 : I/O Window 0 Zero Waite State. If this bit is set to "1", 8bit system I/O accesses occur with zero additional wait states and ZEROWS# signal will be active. bit1 : I/O Window 0 IOCS16# Source. If this bit is set to "0", IOCS16# signal will be generated based on the value of the data size bit. If this bit is set to "1", IOCS16# signal will be generated based on the IOIS16# signal. bit0 : I/O Window 0 data size. "0" indicates 8bit mode, and "1" indicates 16bit mode.
2.2 I/O Address n Start Register Low Byte
Index Index I/O Window 0 : 08h I/O Window 1 : 0Ch Default value : 0000 0000b Read & Write
I/O Window 0 Start Address A7 to A0 bit7 : address 7 bit6 : address 6 bit5 : address 5 bit4 : address 4 bit3 : address 3 bit2 : address 2 bit1 : address 1 bit0 : address 0
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RF5C296/RF5C396L/RB5C396/RF5C396
2.3 I/O Address n Start Register High Byte
Index Index I/O Window 0 : 09h I/O Window 1 : 0Dh Default value : 0000 0000b Read & Write
I/O Window 0 Start Address A15 to A8 bit7 : address 15 bit6 : address 14 bit5 : address 13 bit4 : address 12 bit3 : address 11 bit2 : address 10 bit1 : address 9 bit0 : address 8
2.4 I/O Address n Stop Register Low Byte
Index Index I/O Window 0 : 0Ah I/O Window 1 : 0Eh Default value : 0000 0000b Read & Write
I/O Window 0 Stop Address A7 to A0 bit7 : address 7 bit6 : address 6 bit5 : address 5 bit4 : address 4 bit3 : address 3 bit2 : address 2 bit1 : address 1 bit0 : address 0
2.5 I/O Address n Stop Register High Byte
Index Index I/O Window 0 : 0Bh I/O Window 1 : 0Fh Default value : 0000 0000b Read & Write
I/O Window 0 Stop Address A15 to A8 bit7 : address 15 bit6 : address 14 bit5 : address 13 bit4 : address 12 bit3 : address 11 bit2 : address 10 bit1 : address 9 bit0 : address 8
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RF5C296/RF5C396L/RB5C396/RF5C396
3. Memory Mapping
3.1 System Memory Address n Mapping Start Low Byte Register Index
Index :
Memory Window 0 Memory Window 1 Memory Window 2 Memory Window 3 Memory Window 4
10h
18h
20h
28h
30h
Default value : 0000 0000b bit7 : address 19 bit6 : address 18 bit5 : address 17 bit4 : address 16 bit3 : address 15 bit2 : address 14 bit1 : address 13 bit0 : address 12
Read & Write
3.2 System Memory Address n Mapping Start High Byte Register Index
Index :
Memory Window 0 Memory Window 1 Memory Window 2 Memory Window 3 Memory Window 4
11h
19h
21h
29h
31h
Default value : 0000 0000b
Read & Write
bit7 : Data Size Bit. "0" indicates 8bit mode and "1" indicates 16bit mode. bit6 : Zero Wait State. If this bit is set to "1", an 8bit system memory access occur with zero additional wait states and ZEROWS# signal will be active. The WAIT# signal will override this bit. bit5 : Scratch bit (Unused but intended for reading and writing.) bit4 : Scratch bit (Unused but intended for reading and writing.) bit3 : address 23 bit2 : address 22 bit1 : address 21 bit0 : address 20
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RF5C296/RF5C396L/RB5C396/RF5C396
3.3 System Memory Address n Mapping Stop Low Byte Register
Index :
Memory Window 0 Memory Window 1 Memory Window 2 Memory Window 3 Memory Window 4
12h
1Ah
22h
2Ah
32h
Default value : 0000 0000b bit7 : address 19 bit6 : address 18 bit5 : address 17 bit4 : address 16 bit3 : address 15 bit2 : address 14 bit1 : address 13 bit0 : address 12
Read & Write
3.4 System Memory Address n Mapping Stop High Byte Register
Index :
Memory Window 0 Memory Window 1 Memory Window 2 Memory Window 3 Memory Window 4
13h
1Bh
23h
2Bh
33h
Default value : 0000 0000b bit7 : Wait State Bit 1 bit6 : Wait State Bit 0
wait state bit 1
Read & Write
wait state bit 0
# of additional cycle
# of SYSCLK per access
0 0 1 1
0 1 0 1
standard 16bit cycle 1 2 3
3 4 5 6
bit5 : Reserved bit4 : Reserved bit3 : address 23 bit2 : address 22 bit1 : address 21 bit0 : address 20
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RF5C296/RF5C396L/RB5C396/RF5C396
3.5 Card Memory Offset Address n Low Byte Register
Index :
Memory Window 0 Memory Window 1 Memory Window 2 Memory Window 3 Memory Window 4
14h
1Ch
24h
2Ch
34h
Default value : 0000 0000b bit7 : offset address 19 bit6 : offset address 18 bit5 : offset address 17 bit4 : offset address 16 bit3 : offset address 15 bit2 : offset address 14 bit1 : offset address 13 bit0 : offset address 12
Read & Write
3.6 Card Memory Offset Address n High Byte Register
Index :
Memory Window 0 Memory Window 1 Memory Window 2 Memory Window 3 Memory Window 4
15h
1Dh
25h
2Dh
35h
Default value : 0000 0000b
Read & Write
bit7 : Write Protect Bit. If this bit is set to "1", write operations to the PC Card through the corresponding system memory window are inhibited. bit6 : Reg Active.If this bit is set to "1", accesses to the system memory window will result in attribute memory on PC Card being accessed. bit5 : offset address 25 bit4 : offset address 24 bit3 : offset address 23 bit2 : offset address 22 bit1 : offset address 21 bit0 : offset address 20
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RF5C296/RF5C396L/RB5C396/RF5C396
4. Expansion Function
4.1 Mode Control Register 1
Index : 1Fh Default value : 0000 0000b Read & Write
bit7 : When set to "1", this bit specifies disabling bit7 in the data bus for an I/O address of 377h or 3F7h (at read time). When set to "0", this bit specifies no such disabling. This bit defaults to "0" and can be set independently of bit0. bit6 : In PCMCIA-ATA mode, the value of this bit appears at CA25. bit5 : In PCMCIA-ATA mode, the value of this bit appears at CA24. bit4 : In PCMCIA-ATA mode, the value of this bit appears at CA23. bit3 : In PCMCIA-ATA mode, the value of this bit appears at CA22. bit2 : In PCMCIA-ATA mode, the value of this bit appears at CA21. bit1 : In PCMCIA-ATA mode, if this bit is set to "1", the SPKR# input works as an LED input and IRQ12 works as an open drain LED output. Default value is "0". bit0 : PCMCIA-ATA mode bit. "1" selects PCMCIA-ATA mode and "0" selects PCMCIA mode. Default value is "0".
4.2 Mode Control Register 2
Index : 2Fh Default value : 0000 0000b Read & Write
bit7 to bit6 : DMA Request Selection Bits. DREQ from PC Card is defined according to these 2 bits. Default values are "0".
bit 7 bit 6 01 10 11
DREQ
INPACK#
SPKR#/LED#
IOIS16#
bit5 bit4 bit3
: If this bit is set to "1", DREQ is "L" active. If this bit is set to "0", DREQ is "H" active. Default value is "0". : DMA Mode TC Selection Bit. If this bit is set to "0", IRQ11 works as TC. If this bit is set to "1", IRQ15 works as TC. : Direct 5V/3.3V Switch Enable. If bit4 of Power and RESETDRV Control Register is set to "1", setting this bit to "1" will allow the status of 5VDET/GPI pin to select VCC3EN# or VCC5EN# independently of bit0. Default value is "0".
bit2
: Input Acknowledge Enable. If this bit is set to "1", INPACK# pin function is enabled. If this bit is set to "0", INPACK# is disabled. When the input INPACK# pin signal is active, I/O read data are output to the system data bus only if the input INPACK# pin signal is held at "L". Default value is "0".
bit1 bit0
: IREQ# Sense Selection Bit. If this bit is set to "0", IREQ# is "L"active. If this bit is set to "1", IREQ# is "H"active. Default value is "0". : Voltage Selection Bit. If bit4 of Power and RESETDRV Control Register is set to "1", setting this bit to "1" will set VCC3EN# "L". If bit4 of Power and RESETDRV Control Register setting this bit to "0" will set VCC5EN# "L". Default value is "0".
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RF5C296/RF5C396L/RB5C396/RF5C396
5. I/O Address Remapping
This function is available only in RF5C396. I/O offset address can be set in the following registers. Card I/O address is the summation result of system address and I/O offset address.
5.1 Card I/O Offset Address 0 Low Byte Register
Index : 36h Default value : 0000 0000b Read & Write
bit7 : offset address 7 bit6 : offset address 6 bit5 : offset address 5 bit4 : offset address 4 bit3 : offset address 3 bit2 : offset address 2 bit1 : offset address 1 bit0 : always "0"
5.2 Card I/O Offset Address 0 High Byte Register
Index : 37h Default value : 0000 0000b Read & Write
bit7 : offset address 15 bit6 : offset address 14 bit5 : offset address 13 bit4 : offset address 12 bit3 : offset address 11 bit2 : offset address 10 bit1 : offset address 9 bit0 : offset address 8
5.3 Card I/O Offset Address 1 Low Byte Register
Index : 38h Default value : 0000 0000b Read & Write
bit7 : offset address 7 bit6 : offset address 6 bit5 : offset address 5 bit4 : offset address 4 bit3 : offset address 3 bit2 : offset address 2 bit1 : offset address 1 bit0 : always "0"
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RF5C296/RF5C396L/RB5C396/RF5C396
5.4 Card I/O Offset Address 1 High Byte Register
Index : 39h Default value : 0000 0000b Read & Write
bit7 : offset address 15 bit6 : offset address 14 bit5 : offset address 13 bit4 : offset address 12 bit3 : offset address 11 bit2 : offset address 10 bit1 : offset address 9 bit0 : offset address 8
5.5 Chip Identification Register (Read Only)
Index : 3Ah Default value : 32h (RF5C296), B2h (RF5C396) Read Only Read only register, 32h is read back from RF5C296, B2h is read back from RF5C396.
5.6 Mode Control Register 3
Index : 3Bh Default value : 0000 0000b Read & Write
bit7 to bit2 : Reserved. bit1 : DMA Mode Enable Bit. When this bit is set to "1", the DMA Mode is selected in which DMA-related signals are redefined as described in "DMA Mode". This bit defaults to "0". This bit cannot be set to "1" simultaneously for Slot #0 and Slot #1. bit0 : PCMCIA Interface Disable Bit. If this bit is set to "1", signals shown in the below table are set to "Z", all PCMCIA interface signals are disabled and become "Z". The built-in pull-down resistor is disabled for data bus signals. Slot output signals will be caused to transition to high impedance even when bit 0 is set in the Power and RESETDRV Control Register.
Input Output CD1#, CD2#, BVD1, BVD2, RDY/BSY#, WAIT#, WP, INPACK# CA[25 : 0], CD[15 : 0], CE1#, CE2#, CIORD#, CIOWR#, OE#, REG#, RESET, WE#
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RF5C296/RF5C396L/RB5C396/RF5C396
6. Summary of Internal Register
Slot#0 offset Slot#1 offset Register Name Default Value 7654 to 3210
+00h +01h +02h +03h +04h +05h +06h +07h +08h +09h +0Ah +0Bh +0Ch +0Dh +0Eh +0Fh +10h +11h +12h +13h +14h +15h +16h +17h +18h +19h +1Ah +1Bh +1Ch +1Dh +1Eh
+40h +41h +42h +43h +44h +45h +46h +47h +48h +49h +4Ah +4Bh +4Ch +4Dh +4Eh +4Fh +50h +51h +52h +53h +54h +55h +56h +57h +58h +59h +5Ah +5Bh +5Ch +5Dh +5Eh
Identification and Revision Interface Status Power and RESETDRV Control Interrupt and General Control Card Status Change Card Status Change Interrupt Configuration Address Window Enable I/O Control I/O Address 0 Start Low Byte I/O Address 0 Start High Byte I/O Address 0 Stop Low Byte I/O Address 0 Stop High Byte I/O Address 1 Start Low Byte I/O Address 1 Start High Byte I/O Address 1 Stop Low Byte I/O Address 1 Stop High Byte System Memory Address 0 Mapping Start Low Byte System Memory Address 0 Mapping Start High Byte System Memory Address 0 Mapping Stop Low Byte System Memory Address 0 Mapping Stop High Byte Card Memory Offset Address 0 Low Byte Card Memory Offset Address 0 High Byte Card Detect and General Control Reserved System Memory Address 1 Mapping Start Low Byte System Memory Address 1 Mapping Start High Byte System Memory Address 1 Mapping Stop Low Byte System Memory Address 1 Mapping Stop High Byte Card Memory Offset Address 1 Low Byte Card Memory Offset Address 1 High Byte Global Control
1 0 00
0011
0 1 1 1 1
0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 0 0 0
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RF5C296/RF5C396L/RB5C396/RF5C396
Slot#0 offset
Slot#1 offset
Register Name
Default Value 7654 to 3210
+1Fh +20h +21h +22h +23h +24h +25h +26h +27h +28h +29h +2Ah +2Bh +2Ch +2Dh +2Eh +2Fh +30h +31h +32h +33h +34h +35h +36h +37h +38h +39h +3Ah +3Bh
+5Fh +60h +61h +62h +63h +64h +65h +66h +67h +68h +69h +6Ah +6Bh +6Ch +6Dh +6Eh +6Fh +70h +71h +72h +73h +74h +75h +76h +77h +78h +79h +7Ah +7Bh
Mode Control 1 System Memory Address 2 Mapping Start Low Byte System Memory Address 2 Mapping Start High Byte System Memory Address 2 Mapping Stop Low Byte System Memory Address 2 Mapping Stop High Byte Card Memory Offset Address 2 Low Byte Card Memory Offset Address 2 High Byte Reserved Reserved System Memory Address 3 Mapping Start Low Byte System Memory Address 3 Mapping Start High Byte System Memory Address 3 Mapping Stop Low Byte System Memory Address 3 Mapping Stop High Byte Card Memory Offset Address 3 Low Byte Card Memory Offset Address 3 High Byte Reserved Mode Control 2 System Memory Address 4 Mapping Start Low Byte System Memory Address 4 Mapping Start High Byte System Memory Address 4 Mapping Stop Low Byte System Memory Address 4 Mapping Stop High Byte Card Memory Offset Address 4 Low Byte Card Memory Offset Address 4 High Byte Card I/O Offset Address 0 Low Byte Card I/O Offset Address 0 High Byte Card I/O Offset Address 1 Low Byte Card I/O Offset Address 1 High Byte Chip Identification Mode Control 3
0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
011 0010*
0 000 0000
*)
Chip Identification Register bit7 is read back "0" from RF5C296, "1" from RF5C396.
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RF5C296/RF5C396L/RB5C396/RF5C396
HARDWARE DESIGN CONSIDERATIONS
1. Initial Value Setting Pins
For the RF5C296 and the RF5C396, the SPKROUT#, RI_OUT#, and INTR# pins function as output pins normally but as input pins whose input status determine internal settings during the time that the RESETDRV pin is held at high level as shown in the diagram below.
RESETDRV
SPKROUT# RI_OUT# INTR#
Function as input pins
Function as output pins Pin status capturing
Internal settings can be made by pulling up or down these pins to such a degree as not to affect normal operation (on the order of 10k1/2 for ordinary circuits).
1.1 SPKROUT# and RI_OUT# Pins
The SPKROUT# and RI_OUT# pins determine an index range for access to the internal registers as shown in the table below : * RF5C296
RI_OUT# SPKROUT# Device bit Slot bit Index Range
VDD VDD GND GND
VDD GND VDD GND
0 0 1 1
0 1 0 1
00 to 3Fh 40 to 7Fh 80 to BFh C0 to EFh
* RF5C396
SPKROUT# Device bit Slot bit Index Range
VDD VDD GND GND
0 0 1 1
0 1 0 1
00 to 3Fh 40 to 7Fh 80 to BFh C0 to EFh
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RF5C296/RF5C396L/RB5C396/RF5C396
1.2 INTR# Pin
The INTR# pin determines whether to use external decoding or internal decoding for access to the internal registers. Pulling up and down the INTR# pin specifies internal decoding and external decoding, respectively. For details, see "6. Access to Internal Registers" in "FUNCTIONAL DESCRIPTION".
2. Connections to System Bus
2.1 IOCS16#, MEMCS16#, ZEROWS#, and IOCHRDY Pins
Basically, connections to the ISA bus only require connections to corresponding bus pins. The IOCS16#, MEMCS16#, ZEROWS#, and IOCHRDY pins are open-drain output pins which require an external pull-up resistor in the absence of any pull-up resistor provided on the ISA bus. These resistors are designed to drive a 3001/2 pull-up resistor (for the IOCS16#, MEMCS16#, and ZEROWS# pins) and a 1k1/2 pull-up resistor (for the IOCHRDY). The ZEROWS# and IOCHRDY pins are also caused to transition to "H" level for the maximum duration of one clock pulse upon transition from low level to high impedance as shown in the figure below. Originally, strict regulation of the pull-up resistor for these open-drain output pins is required for the fast rising edge of their pin signals but not recommended in consideration of current consumption. For the RF5C296 and the RF5C396, such unique designs of the ZEROWS# and IOCHRDY pins allow restriction of current consumption without strict regulation of the pull-up resistor to such a degree as not to affect any other system.
SYSCLK One clock pulse
IOCHRDY T21 ZEROWS#
2.2 CS# Pin
The CS# pin is intended to determine an I/O address for access to the control registers for the RF5C296 and the RF5C396 and not directly related to access to the card windows. As described before, either external decoding or internal decoding can be used to determine an I/O address for access to the control registers. (For details, see "6. Access to Internal Registers" in "FUNCTIONAL DESCRIPTION".) When external decoding is used, an I/O address for access to the control registers can be determined by decoding the address signals output from the SA15 to the SA1 (or the SA23 to the SA16 for some systems) for input with negative logic to the CS# pin. When internal decoding is used, access to the internal registers is conditional upon the CS# pin held at "L" and an I/O address of 03E0h or 03E1h. In this case, the CS# pin must receive a signal input which becomes active only when the SA15 to SA10 pins are all caused to transition to "L". This is because the status of the CE# pin affects the Power Down Mode (specified by bit0 in the Global Control Register (Index : 1Eh)). When the Power Down Mode is not in use, therefore, the CE# pin should be held at "L".
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RF5C296/RF5C396L/RB5C396/RF5C396
Whether external decoding or internal decoding is used, note that an address for access to the I/O window (not an address to access to the internal registers) is determined by decoding the address signals output from the SA23 to SA16 pins to (0000 0000)b.
2.3 RESETDRV and POWERGOOD Pins
For the RF5C296 and the RF5C396, reset operation is conditional upon the POWERGOOD pin held at "L"and the RESETDRV pin held at "H". When not in use, therefore, the POWERGOOD pin should be held at "L".
2.4 IRQ12 Pin and LED
Besides connection to the ISA bus, the IRQ12 pin is available in connection to the LED in the PCMCIA_ATA Mode. Direct connection to the LED causes so large a current load to the IRQ12 pin that it should be connected in series to a limiting resistor on the order of 3001/2 to 1k1/2 for connection to the VCC as shown in the figure below. The limiting resistor should be regulated in such a manner that current flowing into the IC core does not exceed 20 mA.
VCC
IRQ12
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RF5C296/RF5C396L/RB5C396/RF5C396
Notes for connecting to System bus except ISA bus
The RF5C296 and the RF5C396 must be connected to any other system bus than the ISA bus in consideration of the following pins: 1) BALE Pin The BALE pin signal is intended to latch the address signals output from the LA23 to LA17 pins because retention of these pin signals is not guaranteed in the entire instruction cycle on the ISA bus. In practice,they are half-latched. The BALE pin may be held at "H", therefore, when the LA23 to LA17 pin signals are retained in the entire instruction cycle on any other bus in the same manner as the SA16 to SA0 2) AEN Pin The AEN pin signal indicates the DMA Mode when held at "H". As such, it should be held at "L" when the DMA Mode is not in use. 3) REFRESH# Pin The REFRESH# pin signal indicates the refresh period of the ISA bus when held at "L". For the RF5C296 and the RF5C396, memory access is conditional upon the REFRESH# pin signal held at "H". The REFRESH# pin signal should be held at "H", therefore, when not in use. 4) SYSCLK Pin The SYSCLK pin signal normally has a frequency of 8.33MHz on the ISA bus. For the RF5C296 and the RF5C396, the SYSCLK pin signal is used for the following five purposes : * Determination of wait time * Determination of the pulse width of the INTR# pin signal * Determination of the reset pulse width of the card states change register in the explicit write back mode. * Bit 0 function of Card Detect and General Control register. * Determination of the high-level duration of the ZEROWS# and IOCHRDY pin signals (For details, see "2.1 IOCS16#, MEMCS16#, ZEROWS#, and IOCHRDY Pins" in "2. Connections to System Bus".) As long as the above purposes can be achieved, the SYSCLK pin signal may be available at a maximum frequency of 11MHz or in DC form.
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3. Connections to PCMCIA Slot
3.1 Pull-up Resistor
The Personal Computer Memory Card Industry Association (PCMCIA) standard requires that some types of pins should be pulled up on the PC card slots. Besides these pins,there are some pins which must be pulled up on the system side. They are listed in the table below.
Pins which must be pulled up Power supply to which pins are pulled up
RDY/BSY#,INPACK#,WAIT#, WP,BVD1,BVD2 CD1#,CD2#,VS1#
(VCC common to card power supply) VCC_AT
For the RF5C296 and the RF5C396, the VSI# pin, which is connected to the 5VDET/GPI pin internally pulled up, requires no external pull-up resistor while the other pins listed above require an external pull-up resistor. For details, see "3.2 5VDET/GPI and VSI# Pins". Basically, the CD1# and CD2# pins should be pulled by a power supply which survives after removal of the PC card from the PC card slot and therefore be confined to the VCC_CORE or the VCC_AT. For the RF5C296 and the RF5C396, in particular, the CD1# and CD2# pins are powered by, and should therefore be pulled up to, the VCC_AT.
3.2 5VDET/GPI and VS1# Pins
Originally, the 5VDET/GPI pin is used as a general-purpose input (GPI) pin capable of generating interrupts upon occurrence of any input change. The VS1# pin is connected to the GND pin on the 3.3V PC card and no connection pin on any other card. The 5VDET/GPI pin, which is internally pulled up as described before, can be connected to the VS1# pin as shown in the figure below to identify whether the PC card supply voltage is 5 or 3.3V.
Power Control Circuits VCC3EN# VCC5EN# VCCSLOT# 5VDET/GPI RF5C296/RF5C396
PCMCIA Card Slot
VCC VS1#
The 5VDET/GPI pin must be connected to the VS1# pin in consideration of the following : * An inverted signal from the 5VDET/GPI pin is read back to bit7 in the Interface Status Register. * Bit2 (GPI Enable Bit) must always be set to "0" in the Card Detect and Control Register. For details on bit7 in the Interface Status Register and bit2 (GPI Enable Bit) in the Card Detect and Control Register, see "6. Access to Internal Registers" in "FUNCTIONAL DESCRIPTION".
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RF5C296/RF5C396L/RB5C396/RF5C396
4. Connections to Power Supply System
4.1 VCC_CORE, VCC_SLOT, and VCC_AT
The RF5C296 and the RF5C396 are designed to supply separate power for the IC core, the ISA bus interface, and the PC card slots from the VCC_CORE, the VCC_AT, and the VCC_SLOT, respectively, as shown in the figure below :
VCC_AT ISA bus Slot#0 VCC_CORE VCC_SLOT#0
Slot#0 Interface ISAbus Interface Core Logic Slot#1 Interface
RF5C296/RF5C396
Slot#1
VCC_SLOT#1
Available power supply combinations are shown in the table below :
Core (VCC_CORE) Card Slot#0 (VCC_SLOT#0) Card Slot#1 (VCC_SLOT#1) ISA bus Interface (VCC_AT)
5V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
5V 5V 3.3V 5V 3.3V 5V 5V 3.3V 3.3V
5V 5V 5V 3.3V 3.3V 5V 3.3V 5V 3.3V
5V 5V 5V 5V 5V 3.3V 3.3V 3.3V 3.3V
As is clear from the above table, the 5V power supply for the IC core (the VCC_CORE) is available in combination with only the 5V peripheral power supplies (the VCC_SLOT#0 for the Card Slot#0, the VCC_SLOT#1 for the Card Slot#1, and the VCC_AT for the ISA bus interface). On the contrary, the 3.3V power supply for the IC core is available in combination with both the 3.3V and 5V peripheral power supplies.
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RF5C296/RF5C396L/RB5C396/RF5C396
The RF5C296 and the RF5C396 are designed to have their power supply system controlled by four output pins : VCC3EN#, VCC5EN#, VPP_EN0, and VPP_EN1. Set the VCC3EN# pin to "0" by controlling the internal register in case of that the 3.3V is supplied to the power supply (VCC_SLOT) of the PC card slots. Set the VCC5EN# pin to "0" by controlling the internal register in case of that the 5.0V is supplied to the power supply (VCC_SLOT) of the PC card slots. Both the VCC3EN# and VCC5EN# cannot be set to "0" simultaneously. Set the VPP_EN0 pin to "1" by controlling the internal register in case of that the VPP (5V) is supplied to the VPP of the PC card slots. Set the VPP_EN1 pin to "1" by controlling the internal register in case of that the VPP (12V) is supplied to the VPP of the PC card slots. Both the VPP_EN0 and VPP_EN1 pins may be set to "1" simultaneously under certain register settings, thus requiring due attention in either hardware or software design. The Intel 82365SL has the four VPP_EN pins and provides separate control over the two power supply pins (VPP1 and VPP2). On the contrary, the RF5C296 and the RF5C396 have the two VPP_EN pins and provide simultaneous control over the VPP1 and VPP2 pins. As an alternative measure, the RF5C296 and the RF5C396 allow separate control over the VPP1 and VPP2 pins by the VPP_EN0 and VPP_EN1 pins, respectively, provided that both the VPP1 and VPP2 must be provided with either the 5V or 12V power supply without fail. These four output pins are controlled by the Power and RESETDRV Control Register (Index : 02h) and the Mixed Voltage Control Register (Index : 2Fh). These pins can be used to configure an external driver for applying voltage to the two power supply pins (VPP1 and VPP2) on the PC card slots. Power supply circuitry for the RF5C296 and the RF5C396 is exemplified in the diagrams below :
12V 5V 3.3V
VPP_EN1 VCC3EN# 5V PC Card VCC PC Card VCC PC Card VPP
VCC5EN#
VPP_EN0
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5. Connecting Multiple Units of RF5C296 or RF5C396
To connect multiple units of the RF5C296 or the RF5C396 to the same system bus, their respective PC card slots must be provided with independent indexes by connecting a pull-up or pull-down resistor to the SPKROUT# and RI_OUT# pins. (For details, see "7. Plural Slot System" in "FUNCTIONAL DESCRIPTION" and "1. Initial Value Setting Pins" in "HARDWARE DESIGN CONSIDERATIONS") Multiple connections to the system bus are wired OR using the IRQn pins. The IRQn pins should be used in consideration of a conflict between interrupt request signals. Driving software for ordinary PC card controllers assigns the same IRQ number to different interrupt signals derived from the PC card status change. Such assignment causes a conflict between interrupt request signals. This problem can be solved by the following three measures : (1) Confining IRQn interrupt request signals derived from the PC card status change to any one unit of the RF5C296 or the RF5C396 and applying polling to the other units at the sacrifice of increased overall current consumption resulting from constant system operation. (2) Re-designing driver software to assign different IRQn pins to interrupt request signals derived from the PC card status change for each IC core at the sacrifice of additional recourse to the IRQn pins which are originally deficient as resources. (3) Connecting the IRQn pins as shown in the diagram below at the sacrifice of additional hardware installation. Basically, the IRQn pins for assigning the same IRQ number to interrupt request signals derived from the PC card status change would be sufficient to implement the hardware configuration shown in the diagram below. In any ordinary system, however, the same IRQ number cannot always be assigned to interrupt request signals derived from the PC card status change, resulting in many cases where circuit change cannot be confined to the single IRQn pin.
IRQn1 IRQn IRQn2 Pull-down resistor on system side
Notice
Under the supply voltage of 3.3V, diode selection requires sufficient care to regulate a voltage drop to a small value.
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RF5C296/RF5C396L/RB5C396/RF5C396
SOFTWARE DESIGN CONSIDERATIONS
1. Confirmation of Access to Internal Registers
The RF5C296 and the RF5C396 contains about fifty 8bit internal registers. One of these internal registers, the Identification and Revision Register (Index : 00h), which is intended for only reading operation and fixed at 83h, is useful for confirming access to the other internal registers.
2. Identification of PC Card Types
One of the initial requirements in inserting the PC card is to identify whether it is the I/O card or the memory card. Such PC card types can be identified by bit5 in the Interrupt and General Control Register (Index : 03h). This bit indicates the I/0 card and the memory card when set to "1" and "0" , respectively.
3. Address Mapping and Address Window Setting
The RF5C296 and the RF5C396 are designed to interface between the CPU bus, such as the ISA bus, and the PC card bus. Unlike ordinary ICs, therefore, these ICs provides address mapping mainly to establish a correspondence between the CPU bus and the PC card bus. In view of such differences, therefore, this section provides separate description of "I/O address mapping" and "memory address mapping".
3.1 I/O Address Space
The I/O address space occupies 64kB ranging from "0000h" to "0FFFFh" on the ISA bus. Similarly, the I/O address space occupies 64kB ranging from "0000h" to "0FFFFh" on the PC card bus, too. The RF5C296 is capable of mapping any given two I/O address windows (ranges) on the ISA bus to the I/O address windows on the PC card bus in units of 1 bytes for each PC card slot in such a manner as to ensure address matching between the ISA bus and the PC card bus. An I/O address window can be set by setting the low-order 8bits of its starting address in the I/O Address n Start Low Byte Register (Index : 08h (I/O Window 0) and 0Ch (I/O Window 1)) and the high-order 8bits in the I/O Address n Start High Byte Register (Index : 09h (I/O Window 0) and 0Dh (I/O Window 1)) while setting the loworder 8bits of its ending address in the I/O Address n Stop Low Byte Register (Index : 0Ah (I/O Window 0) and 0Eh (I/O Window 1)) and the high-order 8bits in the I/O Address n Stop High Byte Register (Index : 0Bh (I/O Window 0) and 0Fh (I/O Window 1)).
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RF5C296/RF5C396L/RB5C396/RF5C396
The RF5C296 provides I/O address mapping as shown in the figure below :
* I/O Address Mapping by RF5C296
I/O address on ISA bus
0000h
I/O address on PC card bus
0000h
aaaah I/O WINDOW 0 bbbbh 03E0h 03E1h cccch I/O WINDOW 1 ddddh
aaaah bbbbh
cccch ddddh
FFFFh
FFFFh I/O address window for access to internal registers (03E0h and 03e1h)(for use in internal decoding)
In the above figure, addresses "03E0h" and "03E1h" form an internal address space for use in internal decoding. On the other hand, the RF5C396 is capable of I/O address mapping in such a manner as to ensure I/O address mismatching between the ISA bus and the PC card bus. The above-described settings of the I/O Address n Start/Stop Low/High Byte Registers for the RF5C296 can be added to the settings of the Card I/O Offset Address n Low/High Byte Registers (Index : 36h (Low-byte Window 0), 37h (High-byte Window 0), 38h (Low-byte Window 1), and 39h (High-byte Window 1)) to form two's complement numbers representing I/O addresses on the PC card bus. The Card I/O Offset Address n Low/High Byte Registers, which always default to "00h", may be omitted from setting to ensure I/O address matching between the ISA bus and the PC card bus in the same manner as for the RF5C296.
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RF5C296/RF5C396L/RB5C396/RF5C396
The RF5C396 provides I/O address mapping as shown in the figure below :
* I/O Address Mapping by RF5C296
I/O address on ISA bus
0000h
I/O address on PC card bus
0000h
aaaah I/O WINDOW 0 bbbbh 03E0h 03E1h cccch I/O WINDOW 1 ddddh
(cccc+f f f f)h (dddd+f f f f)h
(aaaa+eeee)h (bbbb+eeee)h
FFFFh I/O address window for access to internal registers (03E0h and 03e1h)(for use in internal decoding)
FFFFh
The settings of the internal registers relating to I/O address window setting are shown in the table on the next page. For details on the individual internal registers, see "INTERNAL REGISTERS".
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* I/O Address Window Setting
Window 0 Window 1
Index
Start Address
09h : bit7 to 0 08h : bit7 to 0
0Dh : bit7 to 0 0Ch : bit7 to 0
These bits can be used to specify the starting address of the applicable I/O address window. Index
Stop Address
0Bh : bit7 to 0 0Ah : bit7 to 0
0Fh : bit7 to 0 0Eh : bit7 to 0
These bits can be used to specify the ending address of the applicable I/O address window.
Off Set Address (Only RF5C396)
Index
37h : bit7 to 0 36h : bit7 to 0
39h : bit7 to 0 38h : bit7 to 0
These bits can be used to specify the offset address of the applicable I/O address window. Index 07h : bit3 07h : bit7
Wait State
These bits can be used to specify the one wait state (4SYSCLK) 16bit I/O cycle and the standard 16bit I/O cycle when set to "1" and "0", respectively. The 16bit I/O cycle is unavailable in zero wait state form. Index 07h : bit2 07h : bit6
Zero Wait State
These bits can be used to specify the zero wait state 8bit I/O cycle rendering the ZEROWS# pin signal active and the standard 8bit I/O cycle when set to "1" and "0", respectively. Index 07h : bit0 07h : bit4
Data Size
These bits can be used to specify the 8bit mode and the 16bit mode when set to "0" and "1", respectively. Index 07h : bit1 07h : bit5
IOCS16# Source
These bits can be used to specify the dependence of the IOCS16# pin signal on the IOIS16# pin signal from the PC card and on the Data Size Bit when set to "1" and "0", respectively. Index 06h : bit6 06h : bit7
Enable
These bits can be used to specify rendering the applicable I/O window active when set to "1".
The memory address space occupies 16MB ranging from "000000h" to "0FFFFFFh" on the ISA bus. On the contrary, the memory address space occupies 64MB ranging from "0000000h" to "3FFFFFFh" on the PC card bus. The RF5C296 and the RF5C396 are capable of mapping any given five memory address windows (ranges) on the ISA bus to the memory address windows on the PC card bus in units of 4kB for each PC card slot. On the ISA bus, each memory address window ranges from the starting address specified by the System Memory Address n Mapping Start High/Low Byte Registers to the ending address specified by the System Memory Address n Mapping Stop High/Low Byte Registers. On the PC card bus, each memory address window equals to its equivalent on the ISA bus plus the setting of the Card Memory Offset Address n Low Byte Register (forming a two's complement number).
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RF5C296/RF5C396L/RB5C396/RF5C396
Particularly, on the PC card bus, there are two types of memory available : the common memory and the attribute memory, which can be selected by the Card Memory Offset Address n High/Low Byte Registers. The common memory and the attribute memory are used mainly for ordinary access and for storage of such data as PC card information, respectively. During access to the attribute memory, the REG# pin signal is held at "L". The RF5C296 and RF5C396 provide memory address mapping as shown in the figure below :
Memory addresses on ISA bus
000000 h
Memory addresses (in common memory) on PC card bus
Memory addresses (in attribute memory) on PC card bus
000000h
(aaa000)h (bbbFFF)h MEMORY WINDOW 0
(qqqq0 0 0 )h +(c c c 00 0 )h or (qqqq0 0 0 )h +(ddd0 00)h
* * *
(c c c000)h (dddFFF)h MEMORY WINDOW n
* * *
* * *
(pppp 0 00)h +(aaa0 0 0)h or (pppp 00 0)h +(bbbFFF)h
FFFFFF h 16MB memory address space
3FFFFFFh
In the above figure, addresses "(aaa000)h" and "(ccc000)h" can be set in the System Memory Address n Mapping Start High/Low Byte Registers, addresses "(bbbFFF)h" and "(dddFFF)h" in the System Memory Address n Mapping Stop High/Low Byte Registers, and addresses "(pppp000)h" and "(qqqq000)h" in the Card Memory Offset Address n High/Low Byte Registers.
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The settings of the internal registers relating to memory address window setting are shown in the table below. For details on the individual internal registers, see "INTERNAL REGISTERS".
* Memory Address Window Setting
Window 0 Window 1 Window 2 Window 3 Window 4
Start Address
Index
11h : bit3 to 0 10h : bit7 to 0
19h : bit3 to 0 18h : bit7 to 0
21h : bit3 to 0 20h : bit7 to 0
29h : bit3 to 0 28h : bit7 to 0
31h : bit3 to 0 30h : bit7 to 0
These bits can be used to specify the starting address of the applicable memory address window. (A23 to A12)
Stop Address
Index
13h : bit3 to 0 12h : bit7 to 0
1Bh : bit3 to 0 1Ah : bit7 to 0
23h : bit3 to 0 22h : bit7 to 0
2Bh : bit3 to 0 2Ah : bit7 to 0
33h : bit3 to 0 32h : bit7 to 0
These bits can be used to specify the ending address of the applicable memory address window. (A23 to A12) Index 15h : bit5 to 0 14h : bit7 to 0 1Dh : bit5 to 0 1Ch : bit7 to 0 25h : bit5 to 0 24h : bit7 to 0 2Dh : bit5 to 0 2Ch : bit7 to 0 35h : bit5 to 0 34h : bit7 to 0
Offset Address
These bits can be used to specify the offset address of the applicable memory address window. (A25 to A12) Index
Zero Wait State
11h : bit6
19h : bit6
21h : bit6
29h : bit6
31h : bit6
These bits can be used to specify zero wait state access when set to "1" in the 8bit mode, giving first priority to the WAIT# pin signal from the PC card. Index 11h : bit7 19h : bit7 21h : bit7 29h : bit7 31h : bit7
Data Size
These bits can be used to specify 8bit access and 16bit access when set to "0" and "1", respectively. Index 13h : bit7 to 6 1Bh : bit7 to 6 23h : bit7 to 6 2Bh : bit7 to 6 33h : bit7 to 6
These bits can be used to specify memory access cycles, giving first priority to the WAIT# pin signal from the PC card.
bit7 Wait State bit6 # of additional cycle # of SYSCLK per access
0 0 1 1
0 1 0 1
Standard 16bit cycle (additional cycle is "0".) 1 2 3
3 4 5 6
Write Protect
Index
15h : bit7
1Dh : bit7
25h : bit7
2Dh : bit7
35h : bit7
These bits can be used to specify write protection on memory. Index 15h : bit6 1Dh : bit6 25h : bit6 2Dh : bit6 35h : bit6
Reg Active
These bits can be used to specify access to the attribute memory in the IC card when set to "1".
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Window 0
Window 1
Window 2
Window 3
Window 4
Index
MEMCS16#
06h : bit5
This bit can be used to specify the generation of the MEMCS16# pin signal through decoding the A23 to A17 pin signals and through decoding the A23 to A12 pin signals when set to "0" and "1", respectively. Index 06h : bit0 06h : bit1 06h : bit2 06h : bit3 06h : bit4
Window Enable
These bits can be used to specify rendering the applicable memory address window active when set to "1".
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RF5C296/RF5C396L/RB5C396/RF5C396
To enhance understanding of memory access cycles, three types of 16bit memory access cycles are shown in the timing charts below :
(1) Standard Cycle (3 SYSCLK Cycle)
TS SYSCLK MEMR# MEMW# ZEROWS# TC1 TC TS
IOCHRDY
(2) Zero Wait State Cycle (2 SYSCLK Cycle)
TS SYSCLK MEMR# MEMW# ZEROWS# TC TS
IOCHRDY
(3) One Wait State Cycle (4 SYSCLK Cycle)
TS SYSCLK MEMR# MEMW# ZEROWS# TC1 TC1 TC TS
IOCHRDY
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A two or three wait state memory access cycle can be implemented by adding the TC1 in the one wait state memory access cycle of (3). The 16bit memory access cycle is identical to the 16bit I/O cycle in terms of the output timing for the IOCHRDY pin signal except that the latter is unavailable in zero wait state form.
4. Interrupt Processing
The RF5C296 and the RF5C396 generate interrupts derived from the following sources : For I/O Card : Interrupts derived from the IREQ# pin status change : PC Card status change : CD1# and/or CD2# pin status change STSCHG# pin status change (when bit7 is set interrupt and General Control Register (Index : 03h)) 5VDET/GPI pin status change
For Memory Card : PC Card status change : CD1# and/or CD2# pin status change BVD1 and/or BVD2 pin status change READY#/BUSY# pin status change 5VDET/GPI pin status change As shown above, interrupt sources fall into two types : interrupts derived from the IREQ# pin and the PC card status change. Meanwhile, interrupt output destinations available on the ISA bus are the IRQn pins (n = 3, 4, 5, 7, 9, 10, 11, 12, 14, and 15), the INTR# pin, and the RI_OUT# pin (only for interrupts derived from the CD1# and/or CD2# pin status change as specified by bit4 (Card Detect Resume Enable Bit) in the Card Detect and General Control Register (Index : 16h)). Some of the internal registers provide the following four types of interrupt control : (1) Control over interrupt sources (2) Control over interrupt output destinations (3) Control over interrupt output waveforms (4) Control over interrupt cancellation Of the above four types of interrupt control, (1) control over interrupt sources is described in "5. Card Slot Pin Status Indication and Register Setting" while the other three types are described below.
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RF5C296/RF5C396L/RB5C396/RF5C396
4.1 Control over Interrupt Output Destinations
Interrupts derived from the IREQ# pin particularly for the I/O card can be assigned to the IRQn pins as their output destinations by setting bits3 to 0 in the Interrupt and General Control Register (Index : 03h) as shown in the first table on the next page. Interrupts derived from the PC card status change for both the I/O card and the memory card can be assigned to the IRQn pins or the INTR# pin as their output destinations by setting bits7 to 4 in the Card (Index : 03h) as shown in the second table on the next page. Incidentally, the IRQn pins are caused to transition to high impedance unless assigned as interrupt output destinations. As described above, interrupts derived from the CD1# and/or CD2# pin status change among interrupts derived from the PC card status change can be assigned to the RI_OUT# pin as their output destination. More specifically, the RI_OUT# pin output can be generated upon occurrence of the CD1# and/or CD2# pin status change by setting bit4 (Card Detect Resume Enable Bit) to "1" in the Card Detect and General Control Register (Index : 16h) and then setting bit3 (Card Detect Enable Bit) to "1" in the Card Status Interrupt Configuration Register (Index : 05h). For details on these registers, see their respective description in "INTERNAL REGISTERS". Status Interrupt Configuration Register (Index : 05h) or bit4 (INTR# Enable Bit) in the Interrupt and General Control Register
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RF5C296/RF5C396L/RB5C396/RF5C396
* Output Destination Settings for Interrupts Derived from IREQ#
bit3 bit2 bit1 bit0 IRQn Selection
0 0 0 0 0 1 1 1 1 1 1
0 0 1 1 1 0 0 0 1 1 1
0 1 0 0 1 0 1 1 0 1 1
0 1 0 1 1 1 0 1 0 0 1
IRQ not Selected IRQ3 Enabled IRQ4 Enabled IRQ5 Enabled IRQ7 Enabled IRQ9 Enabled IRQ10 Enabled IRQ11 Enabled IRQ12 Enabled IRQ14 Enabled IRQ15 Enabled
* Output Destination Setting for Interrupts Derived from PC Card Status Change
INTR# Enable bit bit7 bit6 bit5 bit4 IRQn Selection
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 1 1 1 1 1 1
0 0 1 1 1 0 0 0 1 1 1
0 1 0 0 1 0 1 1 0 1 1
0 1 0 1 1 1 0 1 0 0 1
IRQ not Selected IRQ3 Enabled IRQ4 Enabled IRQ5 Enabled IRQ7 Enabled IRQ9 Enabled IRQ10 Enabled IRQ11 Enabled IRQ12 Enabled IRQ14 Enabled IRQ15 Enabled redirected to INTR#
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RF5C296/RF5C396L/RB5C396/RF5C396
4.2 Control over Interrupt Output Waveforms
Interrupts derived from the IRQn pins represent different output waveforms in the Level Mode and the Edge Mode. In the Level Mode, the IRQn pin outputs are caused to transition from high impedance to "L" upon interrupt generation and vice versa upon completion of interrupt processing. In the Edge Mode, the IRQn pin outputs are caused to transition from low level to "H" upon interrupt generation and vice versa upon completion of interrupt processing. The Level Mode and the Edge Mode can be specified by setting bit1 (Level Mode Interrupt Enable Bit) to "1" and "0", respectively, in the Global Control Register (Index : 1Eh). Of the IRQn pin outputs, the IRQ14 pin output alone allows exceptional waveform control, which can be specified by setting bit3 (IRQ14 Pulse Mode Enable Bit) to "1" in the Global Control Register (Index : 1Eh). Namely, interrupts derived from the IRQ14 pin represent output waveforms in the Level Mode even when the Edge Mode is specified by setting bit1 (Level Mode Interrupt Enable Bit) to "0" in the Global Control Register (Index : 1Eh). Meanwhile, the INTR# pin output is caused to transition from high level to "L" for the duration of three clock pulses upon interrupt generation and vice versa upon completion of interrupt processing.
4.3 Control over Interrupt Cancellation
Interrupts derived from the IREQ# pin can be canceled by first canceling interrupts on the PC card bus with the IREQ# pin caused to transition to low level and then canceling interrupts on the ISA bus with the IREQ# pin caused to transition to "H". Interrupts derived from the PC card status change can be canceled by the following two methods : (1) Reading the Card Status Change Register (Index : 04h) (2) Setting applicable bits to "1" in the Card Status Change Register (Index : 04h) provided that bit2 (Explicit Write Back Card Status Change Acknowledge Bit) is set to "1" in the Global Control Register (Index : 1Eh).
5. Card Slot Pin Status Indication and Register Setting
The RF5C296 and the RF5C396 have the function of indicating the status of the pins on the PC card slot in various forms to the CPU. This function falls into the following four types : (1) Reading back the pins on the PC card slot (2) Making settings upon occurrence of any pin status change on the PC card slot (3) Generating interrupts upon occurrence of any pin status change on the PC card slot (4) Performing other processes upon occurrence of any pin status change on the PC card slot The internal registers contained in the RF5C296 and the RF5C396 are grouped according to their functions to facilitate such processes as interrupt processing. While the internal registers are described in detail under classification by function in "INTERNAL REGISTERS", they are described briefly under classification by pin on the PC card slot in this section.
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5.1 CD1# and CD2# Pins
The CD1# and CD2# pins are grounded within the PC card and pulled up on the PC card slot. Both the CD1# and CD2# pins are caused to transition to "L" upon insertion of the PC card into the PC card slot. Note that some of the internal registers are designed to control the CD1# and CD2# pins upon occurrence of both the CD1# and CD2# status change and others upon occurrence of either the CD1# or CD2# status change. * Interface Status Register (Index : 01h) : bit3 (for the CD2# pin) and bit2 ( for the CD1# pin) These bits can be used to specify reading back of the CD1# and CD2# pin inputs. * Card Status Change Register (Index : 04h) : bit3 (Card Detect Change bit) This bit will be set to "1" upon occurrence of either the CD1# or CD2# pin status change (insertion or removal of the PC card into or from the PC card slot). * Card Status Interrupt Configuration Register (Index : 05h) : bit3 (Card Detect Enable bit) This bit can be used to specify generation of interrupts from the IRQn pins or the INTR# pin upon occurrence of either the CD1# or CD2# pin status change. * Card Detect and General Control Register (Index : 16h) : bit4 (Card Detect Resume Enable bit) This bit can be used to specify generation of interrupts from the RI_OUT# pin upon occurrence of either the CD1# or CD2# pin status change. * Card Detect and General Control Register (Index : 16h) : bit5 (Software Card Detect Interrupt bit) This bit can be set to "1" to specify software-controlled generation of interrupts derived from the CD1# and/orCD2# pin status change. * Card Detect and General Control Register (Index : 16h) : bit1 (Configuration Reset Enable bit) This bit can be set to "1" to specify generation of reset pulses upon transition of both the CD1# and CD2# pins to "H" (removal of the PC card from the PC card slot), thus resetting the internal registers relating to address windows or interrupts. (For details on the internal registers thus reset, see "1. Chip Control" in "INTERNAL REGISTERS".)
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5.2 BVD1 and BVD2 Pins
The BVD1 and BVD2 pins function as input pins for battery voltage detection when the PC card is the memory card (bit5 is set to "0" in the Interrupt and General Control Register (Index : 03h)). Based on output signals from the PC card, the BVD1 and BVD2 pin signals are defined as shown in the table below :
BVD1 BVD2 Battery voltage conditions
0 0 1 1
0 1 0 1
Faulty battery voltage conditions requiring battery replacement and not guaranteeing data retention. Faulty battery voltage conditions requiring battery replacement and not guaranteeing data retention. Faulty battery voltage conditions requiring battery replacement but guaranteeing data retention. Normal battery voltage conditions.
* Interface Status Register (Index : 01h) : bit1 ( for the BVD2 pin) and bit0 (for the BVD1 pin) These bits can be used to specify reading back the BVD1 and BVD2 pins. * Card Status Change Register (Index : 04h) : bits1 and 0 Bit1 will be se to "1" upon detection of the battery warning condition, respectively. Bit0 will be set to "0" upon detection of the battery dead condition, respectively. * Card Status Interrupt Configuration Register (Index : 05h) : bit1 and bit0 Bit1 can be set to "1" to specify generation of interrupts upon detection of the battery warning conditions, respectively. Bit0 can be set to "1" to specify generation of interrupts upon detection of the battery dead conditions, respectively.
5.3 STSCHG#/RI# Pin
The STSCHG#/RI# pin functions as an input pin for the Card Status Change# and Ring Indicate# signals when the PC card is the I/O card (bit5 is set to "1" in the Interrupt and General Control Register (Index : 03h)). The internal registers described below also function as those relating to the STSCHG#/RI# pin status on the condition that the PC card is the I/O card. * Interface Status Register (Index : 01h) : bit0 (Battery Voltage Detect 1 Bit) This bit can be used to specify reading back the STSCHG#/RI# pin. * Card Status Change Register (Index : 04h) : bit0 This bit will be set to "1" upon transition of the Card Status Change# and RI# signals to "0" when bit7 (Ring Indicate Enable Bit) is set to "0" in the Interrupt and General Control Register (Index : 03h). * Interrupt and General Control Register (Index : 03h) : bit7 (Ring Indicate Enable Bit) This bit can be set to "1" to specify output of the RING INDICATE# signal to the RI_OUT# pin.
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RF5C296/RF5C396L/RB5C396/RF5C396
5.4 5VDET/GPI Pin
The GPI pin, as its full name "general-purpose input pin" suggests, functions as an input pin for general purpose use. Further, it can also be connected to the VS1# pin on the PC card slot to detect the 5V PC card. (For details, see "3.2 5VDET/GPI and VS1# Pins" in "3. Connections to PCMCIA Slot" in "HARDWARE DESIGN CONSIDERATIONS".) * Interface Status Register (Index : 01h) : bit7 This bit can be used to specify reading back the 5VDET/GPI pin. * Card Status Change Register (Index : 04h) : bit4 (GPI Change Bit) This bit will be set to "1" upon generation of interrupts derived from the GPI pin status change when bit2 (GPI Enable Bit) is set to "1" in the Card Detect and General Control Register (Index : 16h). * Card Detect and General Control Register (Index : 16h) : bit3 (GPI Transmission Control Bit) This bit can be set to "1" and "0" to specify generation of interrupts upon transition of the GPI pin from "H" to "L" and vice versa, respectively. * Card Detect and General Control Register (Index : 16h) : bit2 (GPI Enable Bit) This bit can be used to enable interrupts from the GPI pin and set to "1" to specify generation of interrupts upon the GPI input status change.
5.5 READY#/BUSY# Pins
The internal registers described below function as those relating to the READY#/BUSY# pin status on the condition that the PC card is the memory card. * Interface Status Register (Index : 01h) : bit5 (Ready/Busy# Bit) This bit can be set to "0" and "1" to specify reading back the READY#/BUSY# pins, respectively (specify reading back the IREQ# pin when the PC card is the I/O card). * Card Status Change Register (Index : 04h) : bit2 (Ready Change Bit) This bit will be set to "1" upon transition of the READY#/BUSY# pins from "L" to "H". * Card Status Interrupt Configuration Register (Index : 05h) : bit2 (Ready Enable Bit) This bit can be set to "1" to specify generation of interrupts upon transition of the READY#/BUSY# pins from "L" to "H".
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RF5C296/RF5C396L/RB5C396/RF5C396
5.6 Other Pins
WP Pin * Interface Status Register (Index : 01h) : bit4 (Memory Write Protect Bit) This bit an be used to specify reading back the WP pin. Note that write protection will not be enabled even when the WP pin is set to "1" unless Write Protect Bit is set to "1" for each memory address window. Power Supply Status * Interface Status Register (Index : 01h) : bit6(PC card Power Active Bit) This bit an be used to indicate the status of power supply to the PC card slot and set to "0" and "1" to indicate the power-off state (in which both the VCC3VEN# and VCC5VEN# pins are held at high level) and the poweron state, respectively.
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RF5C296/RF5C396L/RB5C396/RF5C396
ABSOLUTE MAXIMUM RATINGS
Symbol Item Condition Ratings Unit
VCC Vte Topr Tstg
Power Supply Voltage Terminal Voltage Operating Temperature Storage Temperature
GND=0V GND=0V
-0.3 to 7 -0.3 to VCC+0.3 -40 to +85 -55 to +125
V V C C
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. Moreover, such values for any two items must not be reached simultaneously. Operation above these absolute maximum ratings may cause degradation or permanent damage to the device. These are stress ratings only and do not necessarily imply functional operation below these limits.
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RF5C296/RF5C396L/RB5C396/RF5C396
DC ELECTRICAL CHARACTERISTICS (Vcc=5V)
Symbol Item Measuring Condition MIN.
Vcc=5V10%, Ta=0 to 70C
Limits Unit TYP. MAX.
VIH VIL VOH1*1 VOH2*2 VOH3*3 VOL1*1 VOL2*2 VOL3*3 VOL4*4 IILK IIL1*5 IIL2*6 IIL3*7 IOZ Iccstd ICC
"H" Input Voltage "L" Input Voltage "H" Output Voltage "H" Output Voltage "H" Output Voltage "L" Output Voltage "L" Output Voltage "L" Output Voltage "L" Output Voltage Input Leakage Current Input Current (Pull-up) Input Current (Pull-down) Input Current (Pull-down) Off Output Leakage Current Stand-by Current Operating Current IOH=-12mA IOH=-8mA IOH=-4mA IOL=12mA IOL=8mA IOL=4mA IOL=16mA VIN=0 to VCC VIN=0 VIN=VCC VIN=VCC VOUT=0 to VCC VIN=0V or VCC VIN=0V or VCC (VCC=5V) VCC, fsysclk=10MHz
2.0 -0.3 2.4 2.4 2.4
VCC+0.3 0.8
V V V V V
0.4 0.4 0.4 0.4 -10 -200 -50 25 50 -10 100 200 +10 10 RF5C296 RF5C396 12 +10
V V V V A A A A A A mA
20
*1) *2) *3) *4) *5) *6) *7)
SD15 to SD0, ZEROWS# IRQn, CA25 to CA0, CD15 to CD0, CE1#, CE2#, CIORD#, CIOWR#, OE#, WE# SPKROUT#, RI_OUT#, INTR#, GPI, VCC3EN#, VCC5EN#, VPP_EN0, VPP_EN1, REG#, RESET IOCS16#, MEMCS16#, IOCHRDY GPI CD15 to CD0 RESETDRV
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RF5C296/RF5C396L/RB5C396/RF5C396
DC ELECTRICAL CHARACTERISTICS (Vcc=3.3V)
Symbol Item Measuring Condition MIN.
Vcc=3.3V0.3V, Ta=0 to 70C
Limits Unit TYP. MAX.
VIH VIL VOH1*1 VOH2*2 VOH3*3 VOL1*1 VOL2*2 VOL3*3 VOL4*4 IILK IIL1*5 IIL2*6 IIL3*7 IOZ Iccstd ICC
"H" Input Voltage "L" Input Voltage "H" Output Voltage "H" Output Voltage "H" Output Voltage "L" Output Voltage "L" Output Voltage "L" Output Voltage "L" Output Voltage Input Leakage Current Input Current (Pull-up) Input Current (Pull-down) Input Current (Pull-down) Off Output Leakage Current Stand-by Current Operating Current IOH=-6mA IOH=-4mA IOH=-2mA IOL=6mA IOL=4mA IOL=2mA IOL=8mA VIN=0 to VCC VIN=0 VIN=VCC VIN=VCC VOUT=0 to VCC VIN=0V or VCC VIN=0V or VCC (VCC=3.3V) VCC, fsysclk=10MHz
2.0 -0.3 2.4 2.4 2.4
VCC+0.3 0.6
V V V V V
0.4 0.4 0.4 0.4 -10 -100 -25 10 25 -10 50 100 +10 10 RF5C296 RF5C396 6 +10
V V V V A A A A A A mA
10
*1) *2) *3) *4) *5) *6) *7)
SD15 to SD0, ZEROWS# IRQn, CA25 to CA0, CD15 to CD0, CE1#, CE2#, CIORD#, CIOWR#, OE#, WE# SPKROUT#, RI_OUT#, INTR#, GPI, VCC3EN#, VCC5EN#, VPP_EN0, VPP_EN1, REG#, RESET IOCS16#, MEMCS16#, IOCHRDY GPI CD15 to CD0 RESETDRV
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RF5C296/RF5C396L/RB5C396/RF5C396
AC ELECTRICAL CHARACTERISTICS
1. 8/16bit Memory Cycle
VCC=5V10%(3.3V0.3V)*2, Ta=0 to 70C, CL=100pF
Limits Symbol Item MIN. MAX. Unit
Tckl Tckh T1 T2 T3 T7a T35 T12 T5a T5b T6a T6b T6c T21a T20 T17 T29a T29b T29c T41 T42 T30a T40 T32a T32b T38 T31
SYSCLK "L" pulse width SYSCLK "H" pulse width LA <23 : 17> setup time to BALE falling BALE pulse width LA <23 : 17> hold time from BALE LA <23 : 17>, SA <17 : 12>, SA0 and SBHE# setup time to MEMR#, MEMW# MEMR#, MEMW# active to falling edge of SYSCLK SA <16 : 0> and SBHE# hold from MEMR#, MEMW# MEMCS16# valid from LA <23 : 17> MEMCS16# valid from SA <16 : 12> MEMCS16# hold from LA <23 : 17> MEMCS16# tri-state from SA <16 : 12> MEMCS16# tri-state from LA <23 : 17> IOCHRDY active from falling edge of SYSCLK IOCHRDY low from MEMR#, MEMW# ZEROWS# active from SA <16 : 12> ZEROWS# hold from MEMR#, MEMW# ZEROWS# tri-state from SA <16 : 12> ZEROWS# tri-state from MEMR#, MEMW# WAIT# active to IOCHRDY inactive WAIT# inactive to IOCHRDY active CA <25 : 0> valid delay from LA <23 : 17>, SA <16 : 0> CA <25 : 0> hold from LA <23 : 17>, SA <16 : 0> OE#, WE# valid from MEMR#, MEMW# with memory delay inhibit OE#, WE# valid from MEMR#, MEMW# 16bit windows OE#, WE# valid from MEMR#, MEMW active CE#, REG# valid from LA <23 : 17>, SA <16 : 0>
45 45 45 50 15 23 15 25 40*1 24(35)*1 0 24(35) 40 24(35)*1 32*1 60 0 55 35 20(30)*1 0 20(30)*1 50 5 27 T35 0 T35+28 24 47(55)
ns ns ns ns ns ns ns ns
ns ns
ns ns ns
ns ns
ns ns ns ns
ns ns
ns ns ns ns ns ns
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RF5C296/RF5C396L/RB5C396/RF5C396
VCC=5V10%(3.3V0.3V)*2, Ta=0 to 70C, CL=100pF
Limits Symbol Item MIN. MAX. Unit
T39 T71 T72 T73 T74 T75 T76
CE#, REG# invalid from LA <23 : 17>, SA <16 : 0> CD <23 : 17> valid delay from SD <15 : 0> when I/O read SD <15 : 0> hold from MEMR# CD <15 : 0> active from LA <23 : 17>, SA <16 : 0> CD <15 : 0> valid delay from SD <15 : 0> when I/O write SD <15 : 0> setup time from falling edge of MEMW# SD <15 : 0> hold time from MEMW#
0
47 (55) 50
ns ns ns
10 47 (55) 50 0 25
ns ns ns ns
*1) *2)
This Timing assumes a load capacitance of 50pF. In the above table, the parenthesized specifications apply when Vcc=3.30.3V. Accordingly, the non-parenthesized specifications alone apply whether Vcc=5V10% or 3.30.3V.
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RF5C296/RF5C396L/RB5C396/RF5C396
* 8/16bit Memory Cycle
Tck1 SYSCLK Tckh
LA(23,17) T1 T2 BALE SA(16,0) SBHE# T3
ADDRESS VALID T71 T72 VALID T75 T76 DATA VALID T7a T35 T12
SD(15,0) (READ DATA)
SD(15,0) (WRITE DATA)
MEMR#,MEMW# T5a T6a,T6c MEMCS16# T5b T21a IOCHRDY T20 T29b ZEROWS# T17 T41 WAIT# T30a CADR(25,0) ADDRESS VALID T40 T42 T29a, T29c T6b
CD(15,0) (READ DATA) T73
DATA VALID T74 T74 T73 DATA VALID T32a, T32b T38
CD(15,0) (WRITE DATA)
OE#,WE# T39 CE1#,CE2#,REG# T31
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RF5C296/RF5C396L/RB5C396/RF5C396
2. 8/16bit I/O Cycle
VCC=5V10% (3.3V0.3V)*2, Ta=0 to 70C, CL=100pF
Symbol
Item
Limits MIN. MAX.
Unit
T1 T2 T45 T46 T7 T12 T5a T5b T19a T19b T20 T21 T41 T42 T28 T29a T29c T30b T40 T33 T38 T31a T31b T39 T34
LA <23 : 17> setup time from to BALE falling BALE pulse width AEN setup time to IOR#, IOW# AEN hold time to IOR#, IOW# LA <23 : 17>, SA <17 : 0> and SBHE setup time to IOR#, IOW# IOCS16# hold time from SA <15 : 0> IOCS16# active from LA <23 : 17> IOCS16# active from SA <16 : 0> IOCS16# hold time from SA <15 : 0> IOCS16# tri-state from SA <15 : 0> IOCHRDY low from IOR#, IOW# IOCHRDY active from falling edge of SYSCLK WAIT# active to IOCHRDY inactive WAIT# inactive to IOCHRDY active ZEROWS# active from 8bit IOR#, IOW# ZEROWS# hold time from IOR#, IOW# ZEROWS# tri-state from IOR#, IOW# active CA <25 : 0> valid delay from LA <23 : 17>, SA <17 : 0> CA <25 : 0> hold time from LA <23 : 17>, SA<17 : 0> CIORD#, CIOWR# valid from IOR#, IOW# CIORD#, CIOWR# inactive from IOR#, IOW# inactive CE#, REG# valid from LA <23 : 17>, SA <17 : 0> CE#, REG# valid from SA <15 : 0> I/O with IOIS16# generated CE#, REG# invalid from LA <23 : 17>, SA <17 : 0> CA <25 : 0> to IOIS16#
45 50 45 25 45 25 40 24(35) 0 40 32*1 24(35)*1 20(30)*1 0 20(30)*1 25 (35) 0 35 50 5 25 0 24 47 (55) 75 0 45 (55) 35
ns ns ns ns ns ns ns ns ns
ns ns ns
ns ns ns ns ns ns ns ns ns ns ns ns ns
*1) *2)
This Timing assumes a load capacitance of 50pF. In the above table, the parenthesized specifications apply when VCC=3.30.3V. Accordingly, the non-parenthesized specifications alone apply whether VCC=5V10% or 3.30.3V.
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Symbol
Item
Limits MIN. MAX.
Unit
T71 T72 T73 T74 T75 T76
CD <15 : 0> valid delay from SD <15 : 0> when I/O read SD <15 : 0> hold time IOR# CD <15 : 0> active from LA <23 : 17>, SA <17 : 0> CD <15 : 0> valid delay from SD <15 : 0> when I/O read SD <15 : 0> setup time to IOW# active SD <15 : 0> hold time IOW# 0 25 10
50
ns ns
45 (55) 50
ns ns ns ns
*1) *2)
This Timing assumes a load capacitance of 50pF. In the above table, the parenthesized specifications apply when VCC=3.30.3V. Accordingly, the non-parenthesized specifications alone apply whether VCC=5V10% or 3.30.3V.
NOTE
Setup time of data to falling edge of CIOWR# (tdsu) depends on setup time of address to IOW# of system (Stdsu). tdsu (min.)=Stdsu-30ns.m
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RF5C296/RF5C396L/RB5C396/RF5C396
* 8/16bit I/O Cycle
Tck1 SYSCLK Tckh
LA(23,17) T1 BALE
T2 T45 T46
AEN
SA(16,0) SBHE# SD(15,0) (READ DATA) T75 SD(15,0) (WRITE DATA) T7 IOR#,IOW# T5a IOCS16# T5b
ADDRESS VALID T71 VALID T76 DATA VALID T35 T12 T72
T19a, T19b
T21 IOCHRDY T20
ZEROWS#
T28 T41 T42 T29a, T29b
WAIT# T30b CADR(25,0) ADDRESS VALID T40
CD(15,0) (READ DATA) CD(15,0) (WRITE DATA) T73
DATA VALID T74 DATA VALID T33 T38 T74 T73
CIORD#,CIOWR# T39 CE1#,CE2#,REG# T31a, T31b
IOIS16#
T34
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RF5C296/RF5C396L/RB5C396/RF5C396
3. Internal 8bits Register Access Cycle
VCC=5V10%(3.3V0.3V),Ta=0 to 70C, CL=100pF
Limits Symbol Item MIN. MAX. Unit
T80 T81 T82 T83 T84 T85 T86 T87 T88 T89
SA <16 : 0>, SBHE# setup time AEN setup time AEN hold time I/O command pulse width SD <7 : 0> write data setup time SD <7 : 0> write data hold time SD <7 : 0> read data delay SD <7 : 0> read data hold time CS# setup time CS# hold time
45 45 25 100 40 10 70 0 100 0
ns ns ns ns ns ns ns ns ns ns
SYSCLK
LA(23,17) T1 BALE
ADDRESS VALID
T80 SA(16,0) SBHE# T81 AEN IOW# IOR# T83 ADDRESS VALID T82
T84 SD7 to 0(WRITE) T86 SD7 to 0(READ) CS# T88
T85
T87
T89
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RF5C296/RF5C396L/RB5C396/RF5C396
4. Interrupt, Ring Indicate Speaker
VCC=5V10%(3.3V0.3V)*1,Ta=0 to 70C, CL=100pF
Limits Symbol Item MIN. MAX. Unit
T50 T51 T52 T53 T54
RI# to RI_OUT# delay, SPKR# to SPKROUT# delay Card Status Change, INTR# valid delay Card Status Change, IRQn valid delay INTR# pulse width IREQ# to IRQn delay 3Tclkp*2
30 2Tclkp*2 50
ns ns ns ns
50
ns
*1) *
In the above table, the parenthesized specifications apply when VCC=3.30.3V. Accordingly, the non-parenthesized specifications alone apply whether VCC=5V10% or 3.30.3V. 2) Tclkp means the clock cycle period.
T50 STSCHG#/RI# T51 Catd Status Change T52 IREQ# T54 INTR# T53 IRQ# T50 RI_OUT# T54
SPKR# T50 SPKROUT# T50
80
RF5C296/RF5C396L/RB5C396/RF5C396
5. Reset from POWERGOOD
VCC=5V10%(3.3V0.3V),Ta=0 to 70C, CL=100pF
Limits Symbol Item MIN. MAX. Unit
T60 T61
RESETDRV setup time to POWERGOOD RESETDRV falling edge from rising edge POWERGOOD
200 5
ns ns
POWERGOOD T60 T61
RESETDRV
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RF5C296/RF5C396L/RB5C396/RF5C396
6. DMA Read Cycle Timing
VCC=5V10%(3.3V0.3V)*2, Ta=0 to 70C, CL=100pF
Limits Symbol Item MIN. MAX. Unit
T41 T42 T33 T38 T74 T91 T92 T93
IOCHRDY inactive from WAIT# active IOCHRDY active to WAIT# inactive CIOWE# active from IOW# IOW# inactive to rising edge of CIOWR#, TC (WE#) SD <15 : 0> valid to CD <15 : 0> valid DACK# (IRQ9) active to DMA cycle begin system TC (IRQ11 or IRQ15) to card TC (WE#) rising edge of DACK# (IRQ9) to CE#, REG# 0 0
20(30)*1 20(30)*1 25 24 50 40 (50) 40 (50) 40 (50)
ns ns ns ns ns ns ns ns
*1) This Timing assumes a load capacitance of 50pF. *2) In the above table, the parenthesized specifications apply when VCC=3.30.3V. Accordingly, the non-parenthesized specifications alone apply whether
VCC=5V10% or 3.30.3V.
IRQ9 (DACK#) SD(15,0) IOW# IOCHRDY
T91 DATA VALID
T93
T41 CIORD#,OE# (high) REG# (DACK# to card) CE1#,CE2# T74 CD(15,0) T33 CIOWR# WAIT# IRQ11 or IRQ15 (TC from system) WE# (TC to card)
T42
T74 DATA VALID T38
T92
82
RF5C296/RF5C396L/RB5C396/RF5C396
7. DMA Write Cycle Timing
VCC=5V10%(3.3V0.3V)*2, Ta=0 to 70C, CL=100pF
Symbol
Item
Limits Unit MIN. MAX.
T41 T42 T33 T38 T71 T72 T94 T95 T96
IOCHRDY inactive from WAIT# active IOCHRDY active from WAIT# inactive CIORD# active from IOR# IOR# inactive to rising edge of CIORD#, TC (OE#) SD <15 : 0> valid to CD <15 : 0> valid SD <15 : 0> hold from IOR#, MEMR# DACK# (IRQ9) active to DMA cycle begin system TC (IRQ11 or IRQ15) to card TC (WE#) rising edge of DACK# (IRQ9) to CE#, REG# 10 0 0
20(30)*1 20(30)*1 25 24 50
ns ns ns ns ns ns
40 (50) 40 (50) 40 (50)
ns ns ns
*1) *2)
This Timing assumes a load capacitance of 50pF. In the above table, the parenthesized specifications apply when VCC=3.30.3V. Accordingly, the non-parenthesized specifications alone apply whether VCC=5V10% or 3.30.3V.
IRQ9 (DACK#) SD(15,0) IOR# IOCHRDY
T94 DATA VALID T71 T38 T72
T96
T41 CIOWR#,WE# (high) REG# (DACK# to card) CE1#,CE2# CD(15,0) T33 CIORD# WAIT# IRQ11 or IRQ15 (TC from system) OE# (TC to card)
T42
DATA VALID
T95
83
RF5C296/RF5C396L/RB5C396/RF5C396
8. DMA Request Timing
VCC=5V10%(3.3V0.3V), Ta=0 to 70C, CL=100pF
Limits Symbol Item MIN. MAX. Unit
T97
DMA request from card to system
40
ns
INPACK#, SPKP#, or IOIS16# (DREQ or DREQ# from card) T97 IRQ10 (DREQ to system)
Notice For the RF5C296 and the RF5C396, the relation between the Read/Write timings for the DATA and ADDRESS signals and those for the CIOWR#, CIORD#, WE#, and OE# signals is not specified, and dependent on the input timings for the relevant signals from the system bus and on the internal delay time of the named signals. It is recommended that the above should be included in the considerations of timing conditions for the JEIDA4.2 (or PCMCIA2.1) system.
84
RF5C296/RF5C396L/RB5C396/RF5C396
BUS SYSTEM
ADDRESS CONTROL
ADDRESS RF5C296 CONTROL RF5C396L RF5C396 DATA
CARD SLOT
ISA BAS
DATA
POWER PWR CTRL SWITCHING
SUPPORT ENVIRONMENT
* Driver Soft Phoenix Technologies,Ltd.(U.S.A.) SystemSoft Corporation(U.S.A.) * Demonstration board Demonstration board for RF5C396 PhoenixCARD Manager PlusTM SystemSoft's Card SoftTM
85
RF5C296/RF5C396L/RB5C396/RF5C396
PACKAGE DIMENSIONS
* RF5C296 144pin LQFP (LQFP-144-P1)
0.15(0.006) M
220.4 0.8660.016 20typ. 0.787typ. 72 73 37
0.150.05 0.0060.002
0
220.4 0.8660.016
20typ. 0.787typ.
0.020
0.5
0.20.1 0.0080.004
36
108 109 144
1
1.5 +0.2 -0.15 0.059 +0.008 -0.006 1.7max. 0.067max.
0.50.2 0.0200.008 0min. 0min. Unit : mm inch
0 t o
* RF5C396L 208pin LQFP (LQFP-208-P1)
0.1(0.004) M
30.00.4 1.1810.016 28.0typ. 1.102typ.
1.0typ. 0.039typ.
0.1(0.004)
10 to
0.1270.05 0.0050.002
10
104 105
53 0.20.1 0.0080.004 0.1(0.004) +0.2 1.4 -0.16 +0.008 0.055 -0.006 1.7max. 0.067max. 0min. 0min. mm inch 0.50.2 0.0200.008 1.0typ. 0.039typ.
30.00.4 1.1810.016
28.0typ. 1.102typ.
1 157 208
0.020
0.5
Unit :
86
RF5C296/RF5C396L/RB5C396/RF5C396
* RB5C396 256pin PBGA (BGA-256-P1)
23.00.4 0.9060.016 19.5typ. 0.768typ. (1.17) (0.046) 1.530.20 0.0600.008 (0.36) (0.014) (0.780.10) (0.0310.004) 23.00.4 0.9060.016 19.5typ. 0.768typ. 4-C1.15 0.600.10 0.0240.004 (2.13) (0.084) 0.25(0.010) M A BCDE FGH J K LMNPR T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1.270.10 0.050.004 mm inch (1.2715=19.05) (0.0515=0.75) 1.980.40 1.270.10 0.0780.016 0.050.004 1.970.40 0.0780.016 (1.2715=19.05) (0.0515=0.75) Unit :
87
RF5C296/RF5C396L/RB5C396/RF5C396
* RF5C396 208pin QFP (QFP-208-P1)
0.1(0.004) M
30.00.4 1.1810.016 28.0typ. 1.102typ.
0 t o
0.150.15 0.0060.002
10
104 105
53 0.20.1 0.0080.004 52 0.1(0.004) +0.2 3.35 -0.16 +0.008 0.132 -0.006 3.8max. 0.150max. Unit : mm inch 1.0typ. 0.039typ. 0min. 0min. 0.50.2 0.0200.008
30.00.4 1.1810.016
28.0typ. 1.102typ.
156 157 208
1
88
0.020
0.5
RICOH COMPANY, LTD. ELECTRONIC DEVICES DIVISION
HEADQUARTERS 13-1, Himemuro-cho, Ikeda City, Osaka 563, JAPAN Phone 81-727-53-1111 Fax 81-727-53-6011 YOKOHAMA OFFICE (International Sales) 3-2-3, Shin-Yokohama, Kohoku-ku, Yokohama City, Kanagawa 222, JAPAN Phone 81-45-477-1697 Fax 81-45-477-1694 *1695
RICOH CORPORATION ELECTRONIC DEVICES DIVISION
SAN JOSE OFFICE 3001 Orchard Parkway, San Jose, CA 95134-2088, U.S.A. Phone 1-408-432-8800 Fax 1-408-432-8375

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